[PATCH] D109889: AMDGPU: Broadcast scalar boolean to vector boolean explicitly

[Jay Foad via Phabricator via llvm-commits]

foad accepted this revision.
foad added a comment.
This revision is now accepted and ready to land.

I think this is OK given that it fixes a bug, and it moves us in the direction of generating explicit bit-broadcasting code instead of relying on the behaviour of i1 COPY instructions.



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Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:4173
+        MRI.getRegClass(CarryDest.getReg());
+    unsigned SelOpc = (TRI->getRegSizeInBits(*CarryDestRC) == 64)
+                          ? AMDGPU::S_CSELECT_B64
----------------
Maybe remember the reg size calculated on line 4141, and reuse it here?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D109889/new/

https://reviews.llvm.org/D109889