[PATCH] D107210: [RISCV] Support interleaved load lowering

[Luke via Phabricator via llvm-commits]

luke957 updated this revision to Diff 375460.
luke957 added a comment.
Herald added a subscriber: achieveartificialintelligence.

Clang tidy


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107210/new/

https://reviews.llvm.org/D107210

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
  llvm/test/Transforms/InterleavedAccess/RISCV/interleaved-accesses.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D107210.375460.patch
Type: text/x-patch
Size: 12528 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20210928/a021d9c5/attachment.bin>