[PATCH] D108129: [DAGCombiner] Teach combineShiftToMULH to handle constant and const splat vector.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:8528
+
+  ConstantSDNode *Constant = isConstOrConstSplat(RightOp);
+  SDValue MulhRightOp;
----------------
Fold this into the if on line 8530 to limit the scope of Constant


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:8533
+    if (IsSignExt) {
+      // If is negative constant, should cout with the signed bit.
+      bool IsSignedConstant = Constant->getAPIntValue().isNegative();
----------------
Why can't we use getMinSignedBits() for signed and getActiveBits() for unsigned.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108129/new/

https://reviews.llvm.org/D108129