[PATCH] D110561: [AArch64] Alter arith-cbz-fusion to fuse between pairs register instructions

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
dmgreen added reviewers: MatzeB, fhahn, t.p.northover, SjoerdMeijer.
Herald added subscribers: hiraditya, kristof.beyls.
dmgreen requested review of this revision.
Herald added a project: LLVM.

There is not a lot of documentation on arith-cbz-fusion in llvm, other than it fuses between arithmetic instructions and cbz branches. It is not explained anywhere that I can find if that is meant to be the arithmetic instruction that defines the register and the cbz that uses it, or any old arithmetic instruction and the branch. The tests seem to suggest it should be the former, but the code only checks for the later.

This updates the code to fuse between the arithmetic instructions setting the register and the cbz using it.


https://reviews.llvm.org/D110561

Files:
  llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
  llvm/test/CodeGen/AArch64/misched-fusion.ll


Index: llvm/test/CodeGen/AArch64/misched-fusion.ll
===================================================================
--- llvm/test/CodeGen/AArch64/misched-fusion.ll
+++ llvm/test/CodeGen/AArch64/misched-fusion.ll
@@ -1,6 +1,7 @@
 ; RUN: llc -o - %s -mtriple=aarch64-unknown -aarch64-enable-cond-br-tune=false -mattr=+arith-bcc-fusion | FileCheck %s --check-prefix=FUSEBCC
 ; RUN: llc -o - %s -mtriple=aarch64-unknown -aarch64-enable-cond-br-tune=false -mattr=+arith-cbz-fusion | FileCheck %s --check-prefix=FUSECBZ
 ; RUN: llc -o - %s -mtriple=aarch64-unknown -aarch64-enable-cond-br-tune=false -mcpu=cyclone            | FileCheck %s --check-prefix=FUSEBCC --check-prefix=FUSECBZ
+; RUN: llc -o - %s -mtriple=aarch64-unknown -aarch64-enable-cond-br-tune=false -mcpu=cortex-a55 -mattr=+arith-bcc-fusion,+arith-cbz-fusion| FileCheck %s --check-prefix=FUSEBCC --check-prefix=FUSECBZ
 
 target triple = "aarch64-unknown"
 
Index: llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
+++ llvm/lib/Target/AArch64/AArch64MacroFusion.cpp
@@ -100,7 +100,7 @@
   case AArch64::SUBWrr:
   case AArch64::SUBXri:
   case AArch64::SUBXrr:
-    return true;
+    return FirstMI->getOperand(0).getReg() == SecondMI.getOperand(0).getReg();
   case AArch64::ADDWrs:
   case AArch64::ADDXrs:
   case AArch64::ANDWrs:
@@ -110,7 +110,8 @@
   case AArch64::BICWrs:
   case AArch64::BICXrs:
     // Shift value can be 0 making these behave like the "rr" variant...
-    return !AArch64InstrInfo::hasShiftedReg(*FirstMI);
+    return !AArch64InstrInfo::hasShiftedReg(*FirstMI) &&
+           FirstMI->getOperand(0).getReg() == SecondMI.getOperand(0).getReg();
   }
 
   return false;


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