[compiler-rt] 354ded6 - tsan: align ThreadState to cache line

[Dmitry Vyukov via llvm-commits]

Author: Dmitry Vyukov
Date: 2021-09-27T12:54:09+02:00
New Revision: 354ded67b30d0f8115dde2f0bbed260d6f4d1b3d

URL: https://github.com/llvm/llvm-project/commit/354ded67b30d0f8115dde2f0bbed260d6f4d1b3d
DIFF: https://github.com/llvm/llvm-project/commit/354ded67b30d0f8115dde2f0bbed260d6f4d1b3d.diff

LOG: tsan: align ThreadState to cache line

There are 2 reasons to do this:
1. We place hot data in the first cache line of ThreadState,
this assumed that it's cache-line-aligned but we never actually
enforced it (or it was lost at some point).
2. The new vector clock uses vector instructions and requires
data alignment. Later the new vector clock will be embedded in
ThreadState, then ensuring vector clock alignment will be
impossible w/o ThreadState alignment.

Depends on D110519.

Reviewed By: melver

Differential Revision: https://reviews.llvm.org/D110520

Added: 
    

Modified: 
    compiler-rt/lib/tsan/rtl/tsan_rtl.cpp
    compiler-rt/lib/tsan/rtl/tsan_rtl.h

Removed: 
    


################################################################################
diff  --git a/compiler-rt/lib/tsan/rtl/tsan_rtl.cpp b/compiler-rt/lib/tsan/rtl/tsan_rtl.cpp
index 23fc49defc8a..d67928224545 100644
--- a/compiler-rt/lib/tsan/rtl/tsan_rtl.cpp
+++ b/compiler-rt/lib/tsan/rtl/tsan_rtl.cpp
@@ -145,6 +145,7 @@ ThreadState::ThreadState(Context *ctx, Tid tid, int unique_id, u64 epoch,
       last_sleep_clock(tid)
 #endif
 {
+  CHECK_EQ(reinterpret_cast<uptr>(this) % SANITIZER_CACHE_LINE_SIZE, 0);
 #if !SANITIZER_GO
   shadow_stack_pos = shadow_stack;
   shadow_stack_end = shadow_stack + kShadowStackSize;

diff  --git a/compiler-rt/lib/tsan/rtl/tsan_rtl.h b/compiler-rt/lib/tsan/rtl/tsan_rtl.h
index b3d2463e3fa6..4f50656a1ea8 100644
--- a/compiler-rt/lib/tsan/rtl/tsan_rtl.h
+++ b/compiler-rt/lib/tsan/rtl/tsan_rtl.h
@@ -223,7 +223,7 @@ struct ThreadState {
   explicit ThreadState(Context *ctx, Tid tid, int unique_id, u64 epoch,
                        unsigned reuse_count, uptr stk_addr, uptr stk_size,
                        uptr tls_addr, uptr tls_size);
-};
+} ALIGNED(SANITIZER_CACHE_LINE_SIZE);
 
 #if !SANITIZER_GO
 #if SANITIZER_MAC || SANITIZER_ANDROID