[PATCH] D110526: [LiveIntervals] Repair subreg ranges in processTiedPairs

[Jay Foad via Phabricator via llvm-commits]

foad created this revision.
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In TwoAddressInstructionPass::processTiedPairs, update subranges of the
live interval for RegB as well as the main range.

This is a small step towards switching TwoAddressInstructionPass over
from LiveVariables to LiveIntervals. Currently this path is only tested
if you explicitly enable -early-live-intervals.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D110526

Files:
  llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
  llvm/test/CodeGen/Hexagon/swp-vect-dotprod.ll
  llvm/test/CodeGen/SystemZ/subregliveness-01.ll
  llvm/test/CodeGen/Thumb2/mve-multivec-spill.ll


Index: llvm/test/CodeGen/Thumb2/mve-multivec-spill.ll
===================================================================
--- llvm/test/CodeGen/Thumb2/mve-multivec-spill.ll
+++ llvm/test/CodeGen/Thumb2/mve-multivec-spill.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -O3 -mattr=+mve %s -o - | FileCheck %s
+; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -O3 -mattr=+mve -early-live-intervals -verify-machineinstrs %s -o - | FileCheck %s
 
 declare void @external_function()
 
Index: llvm/test/CodeGen/SystemZ/subregliveness-01.ll
===================================================================
--- llvm/test/CodeGen/SystemZ/subregliveness-01.ll
+++ llvm/test/CodeGen/SystemZ/subregliveness-01.ll
@@ -1,4 +1,5 @@
 ; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -verify-machineinstrs -systemz-subreg-liveness < %s | FileCheck %s
+; RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -verify-machineinstrs -systemz-subreg-liveness -early-live-intervals < %s | FileCheck %s
 
 ; Check for successful compilation.
 ; CHECK: lgfrl %r0, g_399
Index: llvm/test/CodeGen/Hexagon/swp-vect-dotprod.ll
===================================================================
--- llvm/test/CodeGen/Hexagon/swp-vect-dotprod.ll
+++ llvm/test/CodeGen/Hexagon/swp-vect-dotprod.ll
@@ -1,6 +1,7 @@
 ; RUN: llc -march=hexagon -mcpu=hexagonv5 -enable-pipeliner < %s -pipeliner-experimental-cg=true | FileCheck %s
 ; RUN: llc -march=hexagon -mcpu=hexagonv5 -O2 < %s -pipeliner-experimental-cg=true | FileCheck %s
 ; RUN: llc -march=hexagon -mcpu=hexagonv5 -O3 < %s -pipeliner-experimental-cg=true | FileCheck %s
+; RUN: llc -march=hexagon -mcpu=hexagonv5 -enable-pipeliner < %s -pipeliner-experimental-cg=true -early-live-intervals -verify-machineinstrs | FileCheck %s
 ;
 ; Check that we pipeline a vectorized dot product in a single packet.
 ;
Index: llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
===================================================================
--- llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -1437,6 +1437,10 @@
         SlotIndex endIdx =
             LIS->getInstructionIndex(*MI).getRegSlot(IsEarlyClobber);
         LI.addSegment(LiveInterval::Segment(LastCopyIdx, endIdx, VNI));
+        for (auto &S : LI.subranges()) {
+          VNI = S.getNextValue(LastCopyIdx, LIS->getVNInfoAllocator());
+          S.addSegment(LiveInterval::Segment(LastCopyIdx, endIdx, VNI));
+        }
       }
     }
 


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