[PATCH] D109318: [RISCV][NFC] Refactor classes for load/store instructions of V extension

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:160
 
-// vl<nf>r.v vd, (rs1)
-class VWholeLoad<bits<3> nf, RISCVWidth width, string opcodestr, RegisterClass VRC>
-    : RVInstVLU<nf, width.Value{3}, LUMOPUnitStrideWholeReg,
-                width.Value{2-0}, (outs VRC:$vd), (ins GPR:$rs1),
-                opcodestr, "$vd, (${rs1})"> {
-  let vm = 1;
-  let Uses = [];
-  let RVVConstraint = NoConstraint;
-}
-
 // segment load vd, (rs1), vm
+class VUnitStrideSegmentLoad<bits<3> nf, RISCVWidth width, string opcodestr>
----------------
update the comment to "unit-stride segment load" to sync with above comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:172
 
 // segment load vd, (rs1), rs2, vm
 class VStridedSegmentLoad<bits<3> nf, RISCVWidth width, string opcodestr>
----------------
strided segment load


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:179
 
 // segment load vd, (rs1), vs2, vm
 class VIndexedSegmentLoad<bits<3> nf, RISCVMOP mop, RISCVWidth width,
----------------
indexed segment load


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:189
 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
+// store vd, vs3, (rs1), vm
+class VUnitStrideStore<RISCVWidth width, string opcodestr>
----------------
unit-stride store


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:204
+
 // store vd, vs3, (rs1)
 class VUnitStrideStoreMask<string opcodestr>
----------------
unit-stride masked store


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:211
 
 // store vd, vs3, (rs1), rs2, vm
 class VStridedStore<RISCVWidth width, string opcodestr>
----------------
stride store


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoV.td:217
 
 // store vd, vs3, (rs1), vs2, vm
 class VIndexedStore<RISCVMOP mop, RISCVWidth width, string opcodestr>
----------------
indexed store


Repository:
  rG LLVM Github Monorepo

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https://reviews.llvm.org/D109318