[PATCH] D110505: [X86][Costmodel] Load/store i16 Stride=2 VF=8 interleaving costs

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri created this revision.
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The only sched models that for cpu's that support avx2
but not avx512 are: haswell, broadwell, skylake, zen1-3

For load we have:
https://godbolt.org/z/e5YE99a4P - for intels `Block RThroughput: =6.0`; for ryzens, `Block RThroughput: =2.0`
So pick cost of `6`.

For store we have:
https://godbolt.org/z/3vM4KsE1n - for intels `Block RThroughput: =3.0`; for ryzens, `Block RThroughput: <=2.0`
So pick cost of `3`.

I'm directly using the shuffling asm the llc produced,
without any manual fixups that may be needed
to ensure sequential execution.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D110505

Files:
  llvm/lib/Target/X86/X86TargetTransformInfo.cpp
  llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-2.ll
  llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-2.ll


Index: llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-2.ll
===================================================================
--- llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-2.ll
+++ llvm/test/Analysis/CostModel/X86/interleaved-store-i16-stride-2.ll
@@ -11,7 +11,7 @@
 ; CHECK: LV: Found an estimated cost of 1 for VF 1 For instruction:   store i16 %v1, i16* %out1, align 2
 ; CHECK: LV: Found an estimated cost of 2 for VF 2 For instruction:   store i16 %v1, i16* %out1, align 2
 ; CHECK: LV: Found an estimated cost of 17 for VF 4 For instruction:   store i16 %v1, i16* %out1, align 2
-; CHECK: LV: Found an estimated cost of 49 for VF 8 For instruction:   store i16 %v1, i16* %out1, align 2
+; CHECK: LV: Found an estimated cost of 4 for VF 8 For instruction:   store i16 %v1, i16* %out1, align 2
 ; CHECK: LV: Found an estimated cost of 114 for VF 16 For instruction:   store i16 %v1, i16* %out1, align 2
 ; CHECK: LV: Found an estimated cost of 228 for VF 32 For instruction:   store i16 %v1, i16* %out1, align 2
 ; CHECK-NOT: LV: Found an estimated cost of {{[0-9]+}} for VF {{[0-9]+}} For instruction:   store i16 %v1, i16* %out1, align 2
Index: llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-2.ll
===================================================================
--- llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-2.ll
+++ llvm/test/Analysis/CostModel/X86/interleaved-load-i16-stride-2.ll
@@ -11,7 +11,7 @@
 ; CHECK: LV: Found an estimated cost of 1 for VF 1 For instruction:   %v0 = load i16, i16* %in0, align 2
 ; CHECK: LV: Found an estimated cost of 3 for VF 2 For instruction:   %v0 = load i16, i16* %in0, align 2
 ; CHECK: LV: Found an estimated cost of 17 for VF 4 For instruction:   %v0 = load i16, i16* %in0, align 2
-; CHECK: LV: Found an estimated cost of 41 for VF 8 For instruction:   %v0 = load i16, i16* %in0, align 2
+; CHECK: LV: Found an estimated cost of 7 for VF 8 For instruction:   %v0 = load i16, i16* %in0, align 2
 ; CHECK: LV: Found an estimated cost of 114 for VF 16 For instruction:   %v0 = load i16, i16* %in0, align 2
 ; CHECK: LV: Found an estimated cost of 228 for VF 32 For instruction:   %v0 = load i16, i16* %in0, align 2
 ; CHECK-NOT: LV: Found an estimated cost of {{[0-9]+}} for VF {{[0-9]+}} For instruction:   %v0 = load i16, i16* %in0, align 2
Index: llvm/lib/Target/X86/X86TargetTransformInfo.cpp
===================================================================
--- llvm/lib/Target/X86/X86TargetTransformInfo.cpp
+++ llvm/lib/Target/X86/X86TargetTransformInfo.cpp
@@ -5064,6 +5064,7 @@
   //
   static const CostTblEntry AVX2InterleavedLoadTbl[] = {
       {2, MVT::v2i16, 2}, // (load 4i16 and) deinterleave into 2 x 2i16
+      {2, MVT::v8i16, 6}, // (load 16i16 and) deinterleave into 2 x 8i16
 
       {2, MVT::v4i64, 6}, // (load 8i64 and) deinterleave into 2 x 4i64
 
@@ -5086,6 +5087,7 @@
 
   static const CostTblEntry AVX2InterleavedStoreTbl[] = {
       {2, MVT::v2i16, 1}, // interleave 2 x 2i16 into 4i16 (and store)
+      {2, MVT::v8i16, 3}, // interleave 2 x 8i16 into 16i16 (and store)
 
       {2, MVT::v4i64, 6}, // interleave 2 x 4i64 into 8i64 (and store)
 


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