[PATCH] D110411: [LiveIntervals] Update subranges in processTiedPairs

[Jay Foad via Phabricator via llvm-commits]

foad created this revision.
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In TwoAddressInstructionPass::processTiedPairs when updating live
intervals after moving the last use of RegB back to the newly inserted
copy, update any affected subranges as well as the main range.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D110411

Files:
  llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
  llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll
  llvm/test/CodeGen/Hexagon/addh.ll


Index: llvm/test/CodeGen/Hexagon/addh.ll
===================================================================
--- llvm/test/CodeGen/Hexagon/addh.ll
+++ llvm/test/CodeGen/Hexagon/addh.ll
@@ -1,4 +1,5 @@
 ; RUN: llc -march=hexagon < %s | FileCheck %s
+; RUN: llc -march=hexagon -early-live-intervals -verify-machineinstrs < %s | FileCheck %s
 ; CHECK: r{{[0-9]+}} = add(r{{[0-9]+}}.{{L|l}},r{{[0-9]+}}.{{L|l}})
 
 define i64 @test_cast(i64 %arg0, i16 zeroext %arg1, i16 zeroext %arg2) nounwind readnone {
Index: llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll
===================================================================
--- llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll
+++ llvm/test/CodeGen/AMDGPU/llvm.amdgcn.set.inactive.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
+; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -early-live-intervals -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
 
 define amdgpu_kernel void @set_inactive(i32 addrspace(1)* %out, i32 %in) {
 ; GCN-LABEL: set_inactive:
Index: llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
===================================================================
--- llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -1491,14 +1491,22 @@
 
     // Update LiveIntervals.
     if (LIS) {
-      LiveInterval &LI = LIS->getInterval(RegB);
       SlotIndex MIIdx = LIS->getInstructionIndex(*MI);
-      LiveInterval::const_iterator I = LI.find(MIIdx);
-      assert(I != LI.end() && "RegB must be live-in to use.");
-
       SlotIndex UseIdx = MIIdx.getRegSlot(IsEarlyClobber);
-      if (I->end == UseIdx)
-        LI.removeSegment(LastCopyIdx, UseIdx);
+      LaneBitmask LaneMaskB = TRI->getSubRegIndexLaneMask(SubRegB);
+      auto Shrink = [=](LiveRange &LR, LaneBitmask LaneMask) {
+        if ((LaneMask & LaneMaskB).none())
+          return;
+        LiveRange::const_iterator I = LR.find(MIIdx);
+        assert(I != LR.end() && "RegB must be live-in to use.");
+        if (I->end == UseIdx)
+          LR.removeSegment(LastCopyIdx, UseIdx);
+      };
+
+      LiveInterval &LI = LIS->getInterval(RegB);
+      Shrink(LI, LaneBitmask::getAll());
+      for (auto &S : LI.subranges())
+        Shrink(S, S.LaneMask);
     }
   } else if (RemovedKillFlag) {
     // Some tied uses of regB matched their destination registers, so


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