[PATCH] D110406: Fix incorrect GEP bitwidth in areNonOverlapSameBaseLoadAndStore()
Alexander Richardson via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 24 04:19:39 PDT 2021
arichardson created this revision.
arichardson added reviewers: yamauchi, xbolva00, davidxl.
Herald added subscribers: jrtc27, luismarques, s.egerton, PkmX, simoncook, hiraditya, krytarowski, emaste.
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When using a datalayout that has pointer index width != pointer size this
code triggers an assertion in Value::stripAndAccumulateConstantOffsets().
I encountered this this while compiling FreeBSD for CHERI-RISC-V.
Also update LoadsTest.cpp to use a DataLayout with index width != pointer
width to ensure this case is tested.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D110406
Files:
llvm/lib/Analysis/Loads.cpp
llvm/unittests/Analysis/LoadsTest.cpp
Index: llvm/unittests/Analysis/LoadsTest.cpp
===================================================================
--- llvm/unittests/Analysis/LoadsTest.cpp
+++ llvm/unittests/Analysis/LoadsTest.cpp
@@ -28,6 +28,7 @@
LLVMContext C;
std::unique_ptr<Module> M = parseIR(C,
R"IR(
+target datalayout = "p:64:64:64:32"
%class = type <{ i32, i32 }>
define i32 @f() {
Index: llvm/lib/Analysis/Loads.cpp
===================================================================
--- llvm/lib/Analysis/Loads.cpp
+++ llvm/lib/Analysis/Loads.cpp
@@ -451,8 +451,8 @@
const Value *StorePtr,
Type *StoreTy,
const DataLayout &DL) {
- APInt LoadOffset(DL.getTypeSizeInBits(LoadPtr->getType()), 0);
- APInt StoreOffset(DL.getTypeSizeInBits(StorePtr->getType()), 0);
+ APInt LoadOffset(DL.getIndexTypeSizeInBits(LoadPtr->getType()), 0);
+ APInt StoreOffset(DL.getIndexTypeSizeInBits(StorePtr->getType()), 0);
const Value *LoadBase = LoadPtr->stripAndAccumulateConstantOffsets(
DL, LoadOffset, /* AllowNonInbounds */ false);
const Value *StoreBase = StorePtr->stripAndAccumulateConstantOffsets(
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