[PATCH] D95588: [RISCV] Implement the MC layer support of P extension

[Jim Lin via Phabricator via llvm-commits]

Jim updated this revision to Diff 374748.
Jim added a comment.

1. Rename DecoderNamespace RISCV32Zpsoperand_ -> RISCV32Only_
2. 0.96 -> 0.9.6
3. Use suffices _32 and _64.
4. Reuse RVPBinary and RVPTernary for GPR32PairOp operand
5. Explict list register pair with allocation order


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D95588/new/

https://reviews.llvm.org/D95588

Files:
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
  llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVInstrFormats.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/RISCV/RISCVInstrInfoP.td
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/lib/Target/RISCV/RISCVSubtarget.h
  llvm/lib/Target/RISCV/RISCVSystemOperands.td
  llvm/test/MC/RISCV/rv32zpsfoperand-invalid.s
  llvm/test/MC/RISCV/rv32zpsfoperand-valid.s
  llvm/test/MC/RISCV/rv64zpn-invalid.s
  llvm/test/MC/RISCV/rv64zpn-valid.s
  llvm/test/MC/RISCV/rv64zpsfoperand-invalid.s
  llvm/test/MC/RISCV/rv64zpsfoperand-valid.s
  llvm/test/MC/RISCV/rvp-invalid.s
  llvm/test/MC/RISCV/rvp-non-simd-valid.s
  llvm/test/MC/RISCV/rvp-partial-simd-valid.s
  llvm/test/MC/RISCV/rvp-simd-alu-valid.s
  llvm/test/MC/RISCV/rvp-simd-cmp-valid.s
  llvm/test/MC/RISCV/rvp-simd-misc-valid.s
  llvm/test/MC/RISCV/rvp-simd-mul-valid.s
  llvm/test/MC/RISCV/rvp-simd-shift-valid.s
  llvm/test/MC/RISCV/rvp-simd-unpacking-valid.s

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