[llvm] 661ab70 - [AArch64][GlobalISel] Fix crash in the extend(extract_vector_elt) optimization.

[Amara Emerson via llvm-commits]

Author: Amara Emerson
Date: 2021-09-23T23:07:16-07:00
New Revision: 661ab70314008b609dda792e2c9dc57afa1f8864

URL: https://github.com/llvm/llvm-project/commit/661ab70314008b609dda792e2c9dc57afa1f8864
DIFF: https://github.com/llvm/llvm-project/commit/661ab70314008b609dda792e2c9dc57afa1f8864.diff

LOG: [AArch64][GlobalISel] Fix crash in the extend(extract_vector_elt) optimization.

It was assuming that GPR extends could only have destination sizes of 32 or 64
bits, but for AArch64 we allow < 32 bits even without matching size physregs.

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
    llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt-with-extend.mir

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
index 8961b8085690c..70e2610162efe 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp
@@ -4886,6 +4886,9 @@ bool AArch64InstructionSelector::selectUSMovFromExtend(
   const LLT DstTy = MRI.getType(DefReg);
   unsigned DstSize = DstTy.getSizeInBits();
 
+  if (DstSize != 32 && DstSize != 64)
+    return false;
+
   MachineInstr *Extract = getOpcodeDef(TargetOpcode::G_EXTRACT_VECTOR_ELT,
                                        MI.getOperand(1).getReg(), MRI);
   int64_t Lane;

diff  --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt-with-extend.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt-with-extend.mir
index b2b8fe8c817ff..4e5416a8b8548 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt-with-extend.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt-with-extend.mir
@@ -301,3 +301,18 @@ body: |
     RET_ReallyLR implicit $w0
 
 ...
+---
+name:            skip_anyext_to_16
+legalized:       true
+regBankSelected: true
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    %5:fpr(<16 x s8>) = G_IMPLICIT_DEF
+    %12:gpr(s64) = G_CONSTANT i64 0
+    %4:fpr(s8) = G_EXTRACT_VECTOR_ELT %5(<16 x s8>), %12(s64)
+    %11:gpr(s8) = COPY %4(s8)
+    %8:gpr(s16) = G_ANYEXT %11(s8)
+    %ext:gpr(s32) = G_ANYEXT %8(s16)
+    $w0 = COPY %ext(s32)
+...