[PATCH] D108731: [TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation

[Guozhi Wei via Phabricator via llvm-commits]

Carrot added inline comments.


================
Comment at: llvm/test/CodeGen/X86/addsub-constant-folding.ll:54
 ; X64-NEXT:    callq use at PLT
-; X64-NEXT:    leal 10(%rbx), %eax
+; X64-NEXT:    addl $10, %ebx
+; X64-NEXT:    movl %ebx, %eax
----------------
craig.topper wrote:
> What happened here?
The code before TwoAddress pass is:
```
 %0:gr32 = COPY killed $edi 
  %1:gr32 = ADD32ri8 %0:gr32(tied-def 0), 8, implicit-def dead $eflags
  ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp 
  $edi = COPY killed %1:gr32
  CALL64pcrel32 target-flags(x86-plt) @use, <regmask $bh $bl $bp $bph $bpl $bx $ebp $ebx $hbp $hbx $rbp $rbx $r12 $r13 $r14 $r15 $r12b $r13b $r14b $r15b $r12bh $r13bh $r14bh $r15bh $r12d $r13d $r14d $r15d $r12w $r13w $r14w $r15w $r12wh and 3 more...>, implicit $rsp, implicit $ssp, implicit killed $edi, implicit-def $rsp, implicit-def $ssp
  ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp 
  %2:gr32 = ADD32ri8 killed %0:gr32(tied-def 0), 10, implicit-def dead $eflags
  $eax = COPY killed %2:gr32
  RET 0, killed $eax 
```
Without my patch LLVM generates LEA instructions because function isProfitableToConv3Addr returns true, with my patch function isProfitableToConv3Addr returns false. Although the original code generates good result, the reasoning process is wrong. Function isProfitableToConv3Addr returns true only when the src/dst registers mapped from/to different physical registers. In the ADD instruction we can see %2 is mapped to $eax, %0 is mapped from $edi, this is wrong because of the following instruction prevents coalescing of %0 and $edi.

$edi = COPY killed %1:gr32

With this patch LLVM correctly removes the mapping from %0 to $edi, but it causes worse result because this pass doesn't consider other RA constraints, live range interference in this case. In the ADD instruction now %0 doesn't map from any physical register, so this pass hopes it can be allocated to the same physical register as %2($eax), and keeps the two address ADD instruction. Unfortunately $eax is clobbered by the CALL instruction, so it is interfere with %0, $eax can't be allocated to %0, so the last COPY instruction becomes MOV.



CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D108731/new/

https://reviews.llvm.org/D108731