[llvm] 40b230f - [RISCV] Limit transformAddImmMulImm to prevent an infinite loop.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2021-09-23T15:53:11-07:00
New Revision: 40b230f6856d41f1b8dae7ac2d8e5e5e8de1ca77

URL: https://github.com/llvm/llvm-project/commit/40b230f6856d41f1b8dae7ac2d8e5e5e8de1ca77
DIFF: https://github.com/llvm/llvm-project/commit/40b230f6856d41f1b8dae7ac2d8e5e5e8de1ca77.diff

LOG: [RISCV] Limit transformAddImmMulImm to prevent an infinite loop.

This fixes an issue reported in D108607.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    llvm/test/CodeGen/RISCV/addimm-mulimm.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 55a9e7097238..005f653975dd 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -6416,6 +6416,9 @@ static SDValue transformAddImmMulImm(SDNode *N, SelectionDAG &DAG,
   if (C0 == -1 || C0 == 0 || C0 == 1 || (C1 / C0) == 0 || isInt<12>(C1) ||
       !isInt<12>(C1 % C0) || !isInt<12>(C1 / C0))
     return SDValue();
+  // If C0 * (C1 / C0) is a 12-bit integer, this transform will be reversed.
+  if (isInt<12>(C0 * (C1 / C0)))
+    return SDValue();
   // Build new nodes (add (mul (add x, c1/c0), c0), c1%c0).
   SDLoc DL(N);
   SDValue New0 = DAG.getNode(ISD::ADD, DL, VT, N0->getOperand(0),

diff  --git a/llvm/test/CodeGen/RISCV/addimm-mulimm.ll b/llvm/test/CodeGen/RISCV/addimm-mulimm.ll
index 23b19c9d0e17..fc52c8ab47aa 100644
--- a/llvm/test/CodeGen/RISCV/addimm-mulimm.ll
+++ b/llvm/test/CodeGen/RISCV/addimm-mulimm.ll
@@ -540,3 +540,31 @@ define i64 @add_mul_combine_reject_g3(i64 %x) {
   %tmp1 = add i64 %tmp0, 7310
   ret i64 %tmp1
 }
+
+; This test previously infinite looped in DAG combine.
+define i64 @add_mul_combine_infinite_loop(i64 %x) {
+; RV32IMB-LABEL: add_mul_combine_infinite_loop:
+; RV32IMB:       # %bb.0:
+; RV32IMB-NEXT:    addi a2, zero, 24
+; RV32IMB-NEXT:    mulhu a2, a0, a2
+; RV32IMB-NEXT:    sh1add a1, a1, a1
+; RV32IMB-NEXT:    sh3add a1, a1, a2
+; RV32IMB-NEXT:    sh1add a0, a0, a0
+; RV32IMB-NEXT:    slli a2, a0, 3
+; RV32IMB-NEXT:    addi a0, a2, 1024
+; RV32IMB-NEXT:    addi a0, a0, 1024
+; RV32IMB-NEXT:    sltu a2, a0, a2
+; RV32IMB-NEXT:    add a1, a1, a2
+; RV32IMB-NEXT:    ret
+;
+; RV64IMB-LABEL: add_mul_combine_infinite_loop:
+; RV64IMB:       # %bb.0:
+; RV64IMB-NEXT:    sh1add a0, a0, a0
+; RV64IMB-NEXT:    lui a1, 1
+; RV64IMB-NEXT:    addiw a1, a1, -2048
+; RV64IMB-NEXT:    sh3add a0, a0, a1
+; RV64IMB-NEXT:    ret
+  %tmp0 = mul i64 %x, 24
+  %tmp1 = add i64 %tmp0, 2048
+  ret i64 %tmp1
+}