[llvm] 8811227 - [RISCV] Add more tests for (and (shl x, C2), C1) that can be improved by using a pair of shifts. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2021-09-23T14:18:07-07:00
New Revision: 8811227a0c0ac398857988b4fce0fb4dc699468b

URL: https://github.com/llvm/llvm-project/commit/8811227a0c0ac398857988b4fce0fb4dc699468b
DIFF: https://github.com/llvm/llvm-project/commit/8811227a0c0ac398857988b4fce0fb4dc699468b.diff

LOG: [RISCV] Add more tests for (and (shl x, C2), C1) that can be improved by using a pair of shifts. NFC

These tests have C1 as a shifted mask having no leading zeros and
C3 trailing zeros. If C3 is more than C2, we can select this as
(slli (srli x, C3-C2), C3).

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/shift-and.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/RISCV/shift-and.ll b/llvm/test/CodeGen/RISCV/shift-and.ll
index 9f5bee43ee3ca..8a6de27b47d2b 100644
--- a/llvm/test/CodeGen/RISCV/shift-and.ll
+++ b/llvm/test/CodeGen/RISCV/shift-and.ll
@@ -82,3 +82,44 @@ define i64 @test4(i64 %x) {
   %b = and i64 %a, 288230376151695360
   ret i64 %b
 }
+
+define i32 @test5(i32 %x) {
+; RV32I-LABEL: test5:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    slli a0, a0, 6
+; RV32I-NEXT:    lui a1, 1048560
+; RV32I-NEXT:    and a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: test5:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    slliw a0, a0, 6
+; RV64I-NEXT:    lui a1, 1048560
+; RV64I-NEXT:    and a0, a0, a1
+; RV64I-NEXT:    ret
+  %a = shl i32 %x, 6
+  %b = and i32 %a, -65536
+  ret i32 %b
+}
+
+define i64 @test6(i64 %x) {
+; RV32I-LABEL: test6:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    srli a2, a0, 26
+; RV32I-NEXT:    slli a1, a1, 6
+; RV32I-NEXT:    or a1, a1, a2
+; RV32I-NEXT:    slli a0, a0, 6
+; RV32I-NEXT:    lui a2, 1048560
+; RV32I-NEXT:    and a0, a0, a2
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: test6:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    slli a0, a0, 6
+; RV64I-NEXT:    lui a1, 1048560
+; RV64I-NEXT:    and a0, a0, a1
+; RV64I-NEXT:    ret
+  %a = shl i64 %x, 6
+  %b = and i64 %a, -65536
+  ret i64 %b
+}