[llvm] 4a69551 - [RISCV] Add more isel optimizations for (and (shr x, c2), c1).

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2021-09-23T11:29:04-07:00
New Revision: 4a69551d663e42453c3ad5ab799326fe2ddc9657

URL: https://github.com/llvm/llvm-project/commit/4a69551d663e42453c3ad5ab799326fe2ddc9657
DIFF: https://github.com/llvm/llvm-project/commit/4a69551d663e42453c3ad5ab799326fe2ddc9657.diff

LOG: [RISCV] Add more isel optimizations for (and (shr x, c2), c1).

Turn (and (shr x, c2), c1) -> (slli (srli x, c2+c3), c3) if c1 is a
shifted mask with c2 leading zeros and c3 trailing zeros.

When the leading zeros is C2+32 we can use SRLIW in place of SRLI.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
    llvm/test/CodeGen/RISCV/shift-and.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index b1d6113deff0..25c2989b8691 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -615,7 +615,7 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
       }
     }
 
-    // Turn (and (shl x, c2) c1) -> (srli (slli c2+c3), c3) if c1 is a mask
+    // Turn (and (shl x, c2), c1) -> (srli (slli c2+c3), c3) if c1 is a mask
     // shifted by c2 bits with c3 leading zeros.
     if (LeftShift && isShiftedMask_64(C1)) {
       uint64_t C3 = XLen - (64 - countLeadingZeros(C1));
@@ -645,6 +645,35 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) {
       }
     }
 
+    // Turn (and (shr x, c2), c1) -> (slli (srli x, c2+c3), c3) if c1 is a
+    // shifted mask with c2 leading zeros and c3 trailing zeros.
+    if (!LeftShift && isShiftedMask_64(C1)) {
+      uint64_t Leading = XLen - (64 - countLeadingZeros(C1));
+      uint64_t C3 = countTrailingZeros(C1);
+      if (Leading == C2 && C2 + C3 < XLen && OneUseOrZExtW && !ZExtOrANDI) {
+        SDNode *SRLI = CurDAG->getMachineNode(
+            RISCV::SRLI, DL, XLenVT, X,
+            CurDAG->getTargetConstant(C2 + C3, DL, XLenVT));
+        SDNode *SLLI =
+            CurDAG->getMachineNode(RISCV::SLLI, DL, XLenVT, SDValue(SRLI, 0),
+                                   CurDAG->getTargetConstant(C3, DL, XLenVT));
+        ReplaceNode(Node, SLLI);
+        return;
+      }
+      // If the leading zero count is C2+32, we can use SRLIW instead of SRLI.
+      if (Leading > 32 && (Leading - 32) == C2 && C2 + C3 < 32 &&
+          OneUseOrZExtW && !ZExtOrANDI) {
+        SDNode *SRLIW = CurDAG->getMachineNode(
+            RISCV::SRLIW, DL, XLenVT, X,
+            CurDAG->getTargetConstant(C2 + C3, DL, XLenVT));
+        SDNode *SLLI =
+            CurDAG->getMachineNode(RISCV::SLLI, DL, XLenVT, SDValue(SRLIW, 0),
+                                   CurDAG->getTargetConstant(C3, DL, XLenVT));
+        ReplaceNode(Node, SLLI);
+        return;
+      }
+    }
+
     break;
   }
   case ISD::INTRINSIC_WO_CHAIN: {

diff  --git a/llvm/test/CodeGen/RISCV/shift-and.ll b/llvm/test/CodeGen/RISCV/shift-and.ll
index 9eefb181b94e..9f5bee43ee3c 100644
--- a/llvm/test/CodeGen/RISCV/shift-and.ll
+++ b/llvm/test/CodeGen/RISCV/shift-and.ll
@@ -17,10 +17,8 @@ define i32 @test1(i32 %x) {
 ;
 ; RV64I-LABEL: test1:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    srli a0, a0, 5
-; RV64I-NEXT:    lui a1, 32768
-; RV64I-NEXT:    addiw a1, a1, -8
-; RV64I-NEXT:    and a0, a0, a1
+; RV64I-NEXT:    srliw a0, a0, 8
+; RV64I-NEXT:    slli a0, a0, 3
 ; RV64I-NEXT:    ret
   %a = lshr i32 %x, 5
   %b = and i32 %a, 134217720
@@ -50,16 +48,14 @@ define i64 @test2(i64 %x) {
 define i32 @test3(i32 %x) {
 ; RV32I-LABEL: test3:
 ; RV32I:       # %bb.0:
-; RV32I-NEXT:    srli a0, a0, 6
-; RV32I-NEXT:    lui a1, 16380
-; RV32I-NEXT:    and a0, a0, a1
+; RV32I-NEXT:    srli a0, a0, 20
+; RV32I-NEXT:    slli a0, a0, 14
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: test3:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    srli a0, a0, 6
-; RV64I-NEXT:    lui a1, 16380
-; RV64I-NEXT:    and a0, a0, a1
+; RV64I-NEXT:    srliw a0, a0, 20
+; RV64I-NEXT:    slli a0, a0, 14
 ; RV64I-NEXT:    ret
   %a = lshr i32 %x, 6
   %b = and i32 %a, 67092480
@@ -79,9 +75,8 @@ define i64 @test4(i64 %x) {
 ;
 ; RV64I-LABEL: test4:
 ; RV64I:       # %bb.0:
-; RV64I-NEXT:    srli a0, a0, 6
-; RV64I-NEXT:    lui a1, 1048572
-; RV64I-NEXT:    and a0, a0, a1
+; RV64I-NEXT:    srli a0, a0, 20
+; RV64I-NEXT:    slli a0, a0, 14
 ; RV64I-NEXT:    ret
   %a = lshr i64 %x, 6
   %b = and i64 %a, 288230376151695360