[PATCH] D110305: [TableGen] Allow targets to entirely ignore Psets for registers

[Christudasan Devadasan via Phabricator via llvm-commits]

cdevadas updated this revision to Diff 374545.
cdevadas edited the summary of this revision.
cdevadas added a comment.

Since we liberate the psets for registers now, there is a possibility that targets might skip them entirely.
That shouldn't happen. Added a fatal error to ensure that at least one Pset is generated for the target.
Also, included relevant tests.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D110305/new/

https://reviews.llvm.org/D110305

Files:
  llvm/test/TableGen/bare-minimum-psets.td
  llvm/test/TableGen/empty-psets.td
  llvm/utils/TableGen/CodeGenRegisters.cpp

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