[PATCH] D110328: [LiveIntervals] Repair live intervals that gain subranges

[Jay Foad via Phabricator via llvm-commits]

foad created this revision.
Herald added subscribers: mstorsjo, kerbowa, dmgreen, hiraditya, tpr, nhaehnle, jvesely, MatzeB.
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In repairIntervalsInRange, if the new instructions refer to subregs but
the old instructions did not, make sure any existing live interval for
the superreg is updated to have subranges. Also skip repairing any range
that we have recalculated from scratch, partly for efficiency but also
to avoids some cases that repairOldRegInRange can't handle.

The existing test/CodeGen/AMDGPU/twoaddr-regsequence.mir provides some
test coverage for this change: when TwoAddressInstructionPass converts
REG_SEQUENCE into subreg copies, the live intervals will now get
subranges and MachineVerifier will verify that the subranges are
correct. Unfortunately MachineVerifier does not complain if the
subranges are not present, so the test also passed before this patch.

This patch also fixes ~800 of the ~1500 failures in the whole CodeGen
lit test suite when -early-live-intervals is forced on.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D110328

Files:
  llvm/lib/CodeGen/LiveIntervals.cpp
  llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll
  llvm/test/CodeGen/Hexagon/isel-extload-i1.ll
  llvm/test/CodeGen/Thumb2/mve-ctlz.ll


Index: llvm/test/CodeGen/Thumb2/mve-ctlz.ll
===================================================================
--- llvm/test/CodeGen/Thumb2/mve-ctlz.ll
+++ llvm/test/CodeGen/Thumb2/mve-ctlz.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -verify-machineinstrs -mattr=+mve %s -o - | FileCheck %s
+; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -verify-machineinstrs -mattr=+mve %s -early-live-intervals -verify-machineinstrs -o - | FileCheck %s
 
 define arm_aapcs_vfpcc <2 x i64> @ctlz_2i64_0_t(<2 x i64> %src){
 ; CHECK-LABEL: ctlz_2i64_0_t:
Index: llvm/test/CodeGen/Hexagon/isel-extload-i1.ll
===================================================================
--- llvm/test/CodeGen/Hexagon/isel-extload-i1.ll
+++ llvm/test/CodeGen/Hexagon/isel-extload-i1.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -march=hexagon < %s | FileCheck %s
+; RUN: llc -march=hexagon -early-live-intervals -verify-machineinstrs < %s | FileCheck %s
 
 target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
 target triple = "hexagon"
Index: llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll
===================================================================
--- llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll
+++ llvm/test/CodeGen/AMDGPU/amdgpu-mul24-knownbits.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck --check-prefix=GCN %s
+; RUN: llc -mtriple amdgcn-amd-amdhsa -mcpu=gfx900 -early-live-intervals -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s
 
 define weak_odr amdgpu_kernel void @test_mul24_knownbits_kernel(float addrspace(1)* %p) #4 {
 ; GCN-LABEL: test_mul24_knownbits_kernel:
Index: llvm/lib/CodeGen/LiveIntervals.cpp
===================================================================
--- llvm/lib/CodeGen/LiveIntervals.cpp
+++ llvm/lib/CodeGen/LiveIntervals.cpp
@@ -1677,6 +1677,8 @@
 
   Indexes->repairIndexesInRange(MBB, Begin, End);
 
+  // Make sure a live interval exists for all register operands in the range.
+  SmallVector<Register> RegsToRepair(OrigRegs.begin(), OrigRegs.end());
   for (MachineBasicBlock::iterator I = End; I != Begin;) {
     --I;
     MachineInstr &MI = *I;
@@ -1685,14 +1687,25 @@
     for (MachineInstr::const_mop_iterator MOI = MI.operands_begin(),
                                           MOE = MI.operands_end();
          MOI != MOE; ++MOI) {
-      if (MOI->isReg() && Register::isVirtualRegister(MOI->getReg()) &&
-          !hasInterval(MOI->getReg())) {
-        createAndComputeVirtRegInterval(MOI->getReg());
+      if (MOI->isReg() && MOI->getReg().isVirtual()) {
+        Register Reg = MOI->getReg();
+        // If the new instructions refer to subregs but the old instructions did
+        // not, throw away any old live interval so it will be recomputed with
+        // subranges.
+        if (MOI->getSubReg() && hasInterval(Reg) &&
+            !getInterval(Reg).hasSubRanges() &&
+            MRI->shouldTrackSubRegLiveness(Reg))
+          removeInterval(Reg);
+        if (!hasInterval(MOI->getReg())) {
+          createAndComputeVirtRegInterval(MOI->getReg());
+          // Don't bother to repair a freshly calculated live interval.
+          erase_value(RegsToRepair, Reg);
+        }
       }
     }
   }
 
-  for (Register Reg : OrigRegs) {
+  for (Register Reg : RegsToRepair) {
     if (!Reg.isVirtual())
       continue;
 


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