[PATCH] D110237: [AArch64][SVE] Add DAG combines to improve SVE fixed type FP_EXTEND lowering

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:15242
 
+static SDValue performFpExtendCombine(SDNode *N, SelectionDAG &DAG,
+                                      const AArch64Subtarget *Subtarget) {
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`DAGCombiner::visitFP_EXTEND` tries to do something similar, but unfortunately it is a bit too conservative. Look for:

  // fold (fpext (load x)) -> (fpext (fptrunc (extload x)))

It seems logical to reuse that code, rather than reimplementing the same thing here. Perhaps you can use something like `isVectorLoadExtDesirable` instead of `isLoadExtLegal` to determine whether to fold this.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D110237/new/

https://reviews.llvm.org/D110237