[PATCH] D110250: [RISCV] Sync Zvlsseg register order as the same as vector registers.

[Roger Ferrer Ibanez via Phabricator via llvm-commits]

rogfer01 added a comment.

I think this is reasonable. I wonder if you have a small test that shows we can avoid copies this way. Unless I missed one case, the updates to the tests only show different registers being used (I understand they're small enough and copies are not a problem for them).

Perhaps you can precommit a test that will have better code generation with this change?


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  https://reviews.llvm.org/D110250/new/

https://reviews.llvm.org/D110250