[PATCH] D110305: [TableGen] Allow targets to entirely ignore Psets for registers

[Christudasan Devadasan via Phabricator via llvm-commits]

cdevadas created this revision.
cdevadas added reviewers: atrick, MatzeB, rampitec, arsenm.
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Tablegen currently expects targets to have at least one
pressure set for every broader register category. AMDGPU's
VGPR or AGPR, for instance, seemed to work correctly without
any pset, though we have forced one for each type to avoid
the assertion in `computeRegUnitSets`. This patch bypasses
the assertion for the classes when GeneratePressureSet is zero


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D110305

Files:
  llvm/utils/TableGen/CodeGenRegisters.cpp


Index: llvm/utils/TableGen/CodeGenRegisters.cpp
===================================================================
--- llvm/utils/TableGen/CodeGenRegisters.cpp
+++ llvm/utils/TableGen/CodeGenRegisters.cpp
@@ -2025,7 +2025,8 @@
       }
     }
     LLVM_DEBUG(dbgs() << "\n");
-    assert(!RegClassUnitSets[RCIdx].empty() && "missing unit set for regclass");
+    assert((!RegClassUnitSets[RCIdx].empty() || !RC.GeneratePressureSet) &&
+           "missing unit set for regclass");
   }
 
   // For each register unit, ensure that we have the list of UnitSets that


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