[PATCH] D110300: [RISCV] Sync Zvlsseg register order as the same as vector registers.

[Hsiangkai Wang via Phabricator via llvm-commits]

HsiangKai created this revision.
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Sync the order of Zvlsseg registers with vector registers to avoid
unnecessary register copies between vector instructions and zvlsseg
instructions.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D110300

Files:
  llvm/lib/Target/RISCV/RISCVRegisterInfo.td
  llvm/test/CodeGen/RISCV/rvv/regalloc-fast-crash.ll
  llvm/test/CodeGen/RISCV/rvv/rv32-spill-zvlsseg.ll
  llvm/test/CodeGen/RISCV/rvv/rv64-spill-zvlsseg.ll
  llvm/test/CodeGen/RISCV/rvv/vloxseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vloxseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv32-dead.ll
  llvm/test/CodeGen/RISCV/rvv/vlsegff-rv64-dead.ll
  llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vluxseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsoxseg-rv64.ll
  llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv32.ll
  llvm/test/CodeGen/RISCV/rvv/vsuxseg-rv64.ll