[PATCH] D108129: [DAGCombiner] Teach combineShiftToMULH to handle constant and const splat vector.
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 22 09:36:02 PDT 2021
craig.topper added inline comments.
================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:8519
SDValue RightOp = ShiftOperand.getOperand(1);
+ ConstantSDNode *LeftConstant = isConstOrConstSplat(LeftOp);
+ ConstantSDNode *RightConstant = isConstOrConstSplat(RightOp);
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Do we need to worry about Constant LHS? Won't the mul be canonicalized and then the shift will be revisited?
================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:8535
+ ExtOp.getOperand(0).getValueType().getScalarSizeInBits();
+ unsigned ActiveBits =
+ isConstOrConstSplat(ConstantOp)->getAPIntValue().getActiveBits();
----------------
Isn't ActiveBits the wrong thing to check for SIGN_EXTEND?
================
Comment at: llvm/test/CodeGen/RISCV/rvv/vmulh-sdnode-rv32.ll:69
+; CHECK-NEXT: addi a0, zero, 32
+; CHECK-NEXT: vsrl.vx v25, v25, a0
+; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu
----------------
Was this test case supposed to match to mulh?
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D108129/new/
https://reviews.llvm.org/D108129
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