[PATCH] D110231: [AMDGPU] Add constrained shift pattern matches.

Matt Arsenault via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Sep 22 09:03:59 PDT 2021


arsenm added a comment.

In D110231#3015540 <https://reviews.llvm.org/D110231#3015540>, @foad wrote:

> In D110231#3015515 <https://reviews.llvm.org/D110231#3015515>, @arsenm wrote:
>
>> In D110231#3015225 <https://reviews.llvm.org/D110231#3015225>, @foad wrote:
>>
>>> Would it be better to do this as some kind of DAGCombine, so that other patterns involving shifts (like for v_lshl_add etc instructions) can take advantage of it too? I wonder how other targets do this. I see X86 has isUnneededShiftMask() which is used in PatFrags for shift instruction selection.
>>
>> A combine would be painful because then we have to have custom nodes with these semantics. IIRC X86ISelDAGToDAG does the same basic thing
>
> Fair enough. How about some handy patfrags that we can use in all isel patterns that involve shifts?

That should work


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https://reviews.llvm.org/D110231



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