[PATCH] D109963: [AArch64] Split bitmask immediate of bitwise AND operation

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

I guess there are three options:

- Ignore it, because we believe it will not come up enough in practice enough or will be dealt with elsewhere  (I'm not sure this is always true).
- Teach ISel lowering that the BB is a loop and pick different strategies based on it.
- Do it post-sel in a peephole optimization pass or machine combining pass, that knows about being in a loop or critical patch latencies.

For point 1, the question probably becomes will these cases always be vectorized/unrolled at high optimization levels, in which case it will either be a different (vector) instruction doing most of the work, or the constant would be hoisted by constant hoisting. And when optimizing for size the smaller codesize is probably OK.



================
Comment at: llvm/lib/Target/AArch64/MCTargetDesc/AArch64AddressingModes.h:386
+
+  // Creat a mask which is filled with one from the position of lowest bit set
+  // to the position of highest bit set.
----------------
"Create"


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