[PATCH] D109300: [AMDGPU] Make vector superclasses allocatable

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/GCNRegPressure.cpp:81
+             ? (STI->getRegSizeInBits(*RC) == 32 ? AGPR32 : AGPR_TUPLE)
+             : (STI->getRegSizeInBits(*RC) == 32 ? VGPR32 : VGPR_TUPLE);
 }
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rampitec wrote:
> So for AV and VS it will always tell VGPR? It does not seem conceptually right.
Given the last comment, if we have no real AV operands in any instructions this would be fine.


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Comment at: llvm/lib/Target/AMDGPU/SIFoldOperands.cpp:730
+    // Use VGPR regclass if it is an AV class.
+    if (TRI->isVectorSuperClass(DestRC))
+      MRI->setRegClass(DestReg, TRI->getEquivalentVGPRClass(DestRC));
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Then this shall not be needed because we should not have situations like this.


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Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:11447
+        auto *RC = TRI->getRegClassForReg(MRI, Op.getReg());
+        if (!TRI->hasAGPRs(RC))
           continue;
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And this shall remain as is to not allow any live AV operands.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109300/new/

https://reviews.llvm.org/D109300