[llvm] 7c97566 - [RISCV] Make some arrays of constants 'static const'. NFC
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 21 10:53:18 PDT 2021
Author: Craig Topper
Date: 2021-09-21T10:52:47-07:00
New Revision: 7c975665b47cb91227c5ec0cd902aaf4a7529b58
URL: https://github.com/llvm/llvm-project/commit/7c975665b47cb91227c5ec0cd902aaf4a7529b58
DIFF: https://github.com/llvm/llvm-project/commit/7c975665b47cb91227c5ec0cd902aaf4a7529b58.diff
LOG: [RISCV] Make some arrays of constants 'static const'. NFC
This helps the compiler generate better code.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index a61ded49dc0a..af79b0724b87 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -307,14 +307,14 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::SELECT, XLenVT, Custom);
}
- ISD::CondCode FPCCToExpand[] = {
+ static const ISD::CondCode FPCCToExpand[] = {
ISD::SETOGT, ISD::SETOGE, ISD::SETONE, ISD::SETUEQ, ISD::SETUGT,
ISD::SETUGE, ISD::SETULT, ISD::SETULE, ISD::SETUNE, ISD::SETGT,
ISD::SETGE, ISD::SETNE, ISD::SETO, ISD::SETUO};
- ISD::NodeType FPOpToExpand[] = {
- ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW, ISD::FREM, ISD::FP16_TO_FP,
- ISD::FP_TO_FP16};
+ static const ISD::NodeType FPOpToExpand[] = {
+ ISD::FSIN, ISD::FCOS, ISD::FSINCOS, ISD::FPOW,
+ ISD::FREM, ISD::FP16_TO_FP, ISD::FP_TO_FP16};
if (Subtarget.hasStdExtZfh())
setOperationAction(ISD::BITCAST, MVT::i16, Custom);
@@ -439,13 +439,13 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
- static unsigned IntegerVPOps[] = {
+ static const unsigned IntegerVPOps[] = {
ISD::VP_ADD, ISD::VP_SUB, ISD::VP_MUL, ISD::VP_SDIV, ISD::VP_UDIV,
ISD::VP_SREM, ISD::VP_UREM, ISD::VP_AND, ISD::VP_OR, ISD::VP_XOR,
ISD::VP_ASHR, ISD::VP_LSHR, ISD::VP_SHL};
- static unsigned FloatingPointVPOps[] = {ISD::VP_FADD, ISD::VP_FSUB,
- ISD::VP_FMUL, ISD::VP_FDIV};
+ static const unsigned FloatingPointVPOps[] = {ISD::VP_FADD, ISD::VP_FSUB,
+ ISD::VP_FMUL, ISD::VP_FDIV};
if (!Subtarget.is64Bit()) {
// We must custom-lower certain vXi64 operations on RV32 due to the vector
@@ -593,7 +593,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
// and we pattern-match those back to the "original", swapping operands once
// more. This way we catch both operations and both "vf" and "fv" forms with
// fewer patterns.
- ISD::CondCode VFPCCToExpand[] = {
+ static const ISD::CondCode VFPCCToExpand[] = {
ISD::SETO, ISD::SETONE, ISD::SETUEQ, ISD::SETUGT,
ISD::SETUGE, ISD::SETULT, ISD::SETULE, ISD::SETUO,
ISD::SETGT, ISD::SETOGT, ISD::SETGE, ISD::SETOGE,
More information about the llvm-commits
mailing list