[PATCH] D109963: [AArch64] Split bitmask immediate of bitwise AND operation

[JinGu Kang via Phabricator via llvm-commits]

jaykang10 added inline comments.


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Comment at: llvm/test/CodeGen/AArch64/aarch64-split-and-bitmask-immediate.ll:8
+; CHECK-NEXT:    and w8, w0, #0x3ffc00
+; CHECK-NEXT:    and w8, w8, #0xffe007ff
+; CHECK-NEXT:    cmp w8, #1024
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jaykang10 wrote:
> efriedma wrote:
> > Do we want to do something different if the operation is in a loop, so the immediate could be hoisted?
> um... I do not think the split bitmask immediate affects MachineLICM pass to detect the invariant code.
> 
> Let me add a test case with loop. 
um... I understand it now...

If instruction has register operand and its definition is in loop, the instruction is not loop invariant in MachineLoop...

`AND[W|X]ri` has register operand rather than `MOVi32imm`...

um... Thanks @efriedma. Let me think about it more...


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  https://reviews.llvm.org/D109963/new/

https://reviews.llvm.org/D109963