[PATCH] D109889: AMDGPU: Lower one copy from SCC early for SelectionDAG

[Jay Foad via Phabricator via llvm-commits]

foad added a comment.

In D109889#3012754 <https://reviews.llvm.org/D109889#3012754>, @arsenm wrote:

> In D109889#3012452 <https://reviews.llvm.org/D109889#3012452>, @foad wrote:
>
>>> In SelectionDAG path, we are currently using -1/0 when copying from SCC.
>>> But in GlobalISel path, we are requesting 1/0 when copying from SCC.
>>
>> Is there a good reason for that difference? Is it related to TargetLowering::setBooleanContents? We always set ZeroOrOneBooleanContent for GCN subtargets.
>
> The problem is "COPY from SCC" by itself is not a semantically meaningful concept. We can make up whatever we want. I think ZeroOrOneBooleanContent is a better choice, since it's not fighting an uphill battle for optimization priority, and there really is only one bit. Places that semantically need to use -1 can emit the select directly.

My understanding is that the TargetLowering::setBooleanContents stuff only affects instruction selection, but at instruction selection time we keep all booleans as i1, so the point is moot. It's only after ISel in SILowerI1Copies that we expand booleans to full sgpr width, and yes we can decide to do whatever we want, but I think 0/-1 makes more sense than 0/1 because it matches how we represent divergent i1 values with a bit per lane.


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