[llvm] 3500e7d - [AMDGPU][MC][GFX7][GFX10] Corrected image_atomic_fcmpswap

Dmitry Preobrazhensky via llvm-commits llvm-commits at lists.llvm.org
Tue Sep 21 08:05:40 PDT 2021 

Author: Dmitry Preobrazhensky
Date: 2021-09-21T18:06:02+03:00
New Revision: 3500e7d2b0f1c3f508f384ba9223e879c103b0ab

URL: https://github.com/llvm/llvm-project/commit/3500e7d2b0f1c3f508f384ba9223e879c103b0ab
DIFF: https://github.com/llvm/llvm-project/commit/3500e7d2b0f1c3f508f384ba9223e879c103b0ab.diff

LOG: [AMDGPU][MC][GFX7][GFX10] Corrected image_atomic_fcmpswap

Differential Revision: https://reviews.llvm.org/D109616

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/MIMGInstructions.td
    llvm/test/MC/AMDGPU/gfx10_asm_mimg.s
    llvm/test/MC/AMDGPU/gfx7_asm_mimg.s
    llvm/test/MC/Disassembler/AMDGPU/gfx10_mimg.txt

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/MIMGInstructions.td b/llvm/lib/Target/AMDGPU/MIMGInstructions.td
index 288cf6b02f9ff..c5d0cf830d8fb 100644
--- a/llvm/lib/Target/AMDGPU/MIMGInstructions.td
+++ b/llvm/lib/Target/AMDGPU/MIMGInstructions.td
@@ -959,7 +959,7 @@ defm IMAGE_ATOMIC_OR            : MIMG_Atomic <mimgopc<0x19>, "image_atomic_or">
 defm IMAGE_ATOMIC_XOR           : MIMG_Atomic <mimgopc<0x1a>, "image_atomic_xor">;
 defm IMAGE_ATOMIC_INC           : MIMG_Atomic <mimgopc<0x1b>, "image_atomic_inc">;
 defm IMAGE_ATOMIC_DEC           : MIMG_Atomic <mimgopc<0x1c>, "image_atomic_dec">;
-defm IMAGE_ATOMIC_FCMPSWAP      : MIMG_Atomic <mimgopc<0x1d, MIMG.NOP>, "image_atomic_fcmpswap", 0, 1>;
+defm IMAGE_ATOMIC_FCMPSWAP      : MIMG_Atomic <mimgopc<0x1d, MIMG.NOP>, "image_atomic_fcmpswap", 1, 1>;
 defm IMAGE_ATOMIC_FMIN          : MIMG_Atomic <mimgopc<0x1e, MIMG.NOP>, "image_atomic_fmin", 0, 1>;
 defm IMAGE_ATOMIC_FMAX          : MIMG_Atomic <mimgopc<0x1f, MIMG.NOP>, "image_atomic_fmax", 0, 1>;
 

diff  --git a/llvm/test/MC/AMDGPU/gfx10_asm_mimg.s b/llvm/test/MC/AMDGPU/gfx10_asm_mimg.s
index d8ac36c95aead..4dec236dc7649 100644
--- a/llvm/test/MC/AMDGPU/gfx10_asm_mimg.s
+++ b/llvm/test/MC/AMDGPU/gfx10_asm_mimg.s
@@ -139,6 +139,126 @@ image_atomic_dec v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D glc
 image_atomic_fcmpswap v[4:5], v32, s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_1D glc
 ; GFX10: image_atomic_fcmpswap v[4:5], v32, s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_1D glc ; encoding: [0x00,0x23,0x74,0xf0,0x20,0x04,0x18,0x00]
 
+image_atomic_fcmpswap v[254:255], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm
+; GFX10: [0x00,0x13,0x74,0xf0,0x02,0xfe,0x03,0x00]
+
+image_atomic_fcmpswap v[1:4], v2, s[12:19] dmask:0xf dim:SQ_RSRC_IMG_1D unorm
+; GFX10: [0x00,0x1f,0x74,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_fcmpswap v[252:255], v2, s[12:19] dmask:0xf dim:SQ_RSRC_IMG_1D unorm
+; GFX10: [0x00,0x1f,0x74,0xf0,0x02,0xfc,0x03,0x00]
+
+image_atomic_fcmpswap v[1:2], v255, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm
+; GFX10: [0x00,0x13,0x74,0xf0,0xff,0x01,0x03,0x00]
+
+image_atomic_fcmpswap v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm a16
+; GFX10: [0x00,0x13,0x74,0xf0,0x02,0x01,0x03,0x40]
+
+image_atomic_fcmpswap v[1:2], v255, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm a16
+; GFX10: [0x00,0x13,0x74,0xf0,0xff,0x01,0x03,0x40]
+
+image_atomic_fcmpswap v[1:2], v[2:4], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_3D unorm
+; GFX10: [0x10,0x13,0x74,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_fcmpswap v[1:2], v[253:255], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_3D unorm
+; GFX10: [0x10,0x13,0x74,0xf0,0xfd,0x01,0x03,0x00]
+
+image_atomic_fcmpswap v[1:2], v[2:3], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_3D unorm a16
+; GFX10: [0x10,0x13,0x74,0xf0,0x02,0x01,0x03,0x40]
+
+image_atomic_fcmpswap v[1:2], v[254:255], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_3D unorm a16
+; GFX10: [0x10,0x13,0x74,0xf0,0xfe,0x01,0x03,0x40]
+
+image_atomic_fcmpswap v[1:2], v[2:5], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm
+; GFX10: [0x38,0x13,0x74,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_fcmpswap v[1:2], v[252:255], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm
+; GFX10: [0x38,0x13,0x74,0xf0,0xfc,0x01,0x03,0x00]
+
+image_atomic_fcmpswap v[1:2], v[2:3], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16
+; GFX10: [0x38,0x13,0x74,0xf0,0x02,0x01,0x03,0x40]
+
+image_atomic_fcmpswap v[1:2], v[254:255], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16
+; GFX10: [0x38,0x13,0x74,0xf0,0xfe,0x01,0x03,0x40]
+
+image_atomic_fcmpswap v[1:2], v[2:3], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_2D unorm
+; GFX10: [0x08,0x13,0x74,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_fcmpswap v[1:2], v[254:255], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_2D unorm
+; GFX10: [0x08,0x13,0x74,0xf0,0xfe,0x01,0x03,0x00]
+
+image_atomic_fcmpswap v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_2D unorm a16
+; GFX10: [0x08,0x13,0x74,0xf0,0x02,0x01,0x03,0x40]
+
+image_atomic_fcmpswap v[1:2], v255, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_2D unorm a16
+; GFX10: [0x08,0x13,0x74,0xf0,0xff,0x01,0x03,0x40]
+
+image_atomic_fcmpswap v[1:2], v[2:4], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_CUBE unorm
+; GFX10: [0x18,0x13,0x74,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_fcmpswap v[1:2], v[253:255], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_CUBE unorm
+; GFX10: [0x18,0x13,0x74,0xf0,0xfd,0x01,0x03,0x00]
+
+image_atomic_fcmpswap v[1:2], v[2:3], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_CUBE unorm a16
+; GFX10: [0x18,0x13,0x74,0xf0,0x02,0x01,0x03,0x40]
+
+image_atomic_fcmpswap v[1:2], v[254:255], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_CUBE unorm a16
+; GFX10: [0x18,0x13,0x74,0xf0,0xfe,0x01,0x03,0x40]
+
+image_atomic_fcmpswap v[1:2], v[2:3], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY unorm
+; GFX10: [0x20,0x13,0x74,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_fcmpswap v[1:2], v[254:255], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY unorm
+; GFX10: [0x20,0x13,0x74,0xf0,0xfe,0x01,0x03,0x00]
+
+image_atomic_fcmpswap v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY unorm a16
+; GFX10: [0x20,0x13,0x74,0xf0,0x02,0x01,0x03,0x40]
+
+image_atomic_fcmpswap v[1:2], v255, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY unorm a16
+; GFX10: [0x20,0x13,0x74,0xf0,0xff,0x01,0x03,0x40]
+
+image_atomic_fcmpswap v[1:2], v[2:4], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY unorm
+; GFX10: [0x28,0x13,0x74,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_fcmpswap v[1:2], v[253:255], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY unorm
+; GFX10: [0x28,0x13,0x74,0xf0,0xfd,0x01,0x03,0x00]
+
+image_atomic_fcmpswap v[1:2], v[2:3], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY unorm a16
+; GFX10: [0x28,0x13,0x74,0xf0,0x02,0x01,0x03,0x40]
+
+image_atomic_fcmpswap v[1:2], v[254:255], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY unorm a16
+; GFX10: [0x28,0x13,0x74,0xf0,0xfe,0x01,0x03,0x40]
+
+image_atomic_fcmpswap v[1:2], v[2:4], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA unorm
+; GFX10: [0x30,0x13,0x74,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_fcmpswap v[1:2], v[253:255], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA unorm
+; GFX10: [0x30,0x13,0x74,0xf0,0xfd,0x01,0x03,0x00]
+
+image_atomic_fcmpswap v[1:2], v[2:3], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA unorm a16
+; GFX10: [0x30,0x13,0x74,0xf0,0x02,0x01,0x03,0x40]
+
+image_atomic_fcmpswap v[1:2], v[254:255], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA unorm a16
+; GFX10: [0x30,0x13,0x74,0xf0,0xfe,0x01,0x03,0x40]
+
+image_atomic_fcmpswap v[1:2], v2, s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm
+; GFX10: [0x00,0x13,0x74,0xf0,0x02,0x01,0x18,0x00]
+
+image_atomic_fcmpswap v[1:2], v2, ttmp[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm
+; GFX10: [0x00,0x13,0x74,0xf0,0x02,0x01,0x1d,0x00]
+
+image_atomic_fcmpswap v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc
+; GFX10: [0x00,0x33,0x74,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_fcmpswap v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm slc
+; GFX10: [0x00,0x13,0x74,0xf2,0x02,0x01,0x03,0x00]
+
+image_atomic_fcmpswap v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm dlc
+; GFX10: [0x80,0x13,0x74,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_fcmpswap v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm lwe
+; GFX10: [0x00,0x13,0x76,0xf0,0x02,0x01,0x03,0x00]
+
 image_atomic_fmin v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D glc
 ; GFX10: image_atomic_fmin v4, v32, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D glc ; encoding: [0x00,0x21,0x78,0xf0,0x20,0x04,0x18,0x00]
 

diff  --git a/llvm/test/MC/AMDGPU/gfx7_asm_mimg.s b/llvm/test/MC/AMDGPU/gfx7_asm_mimg.s
index 0335654ef22e3..632a4fce4cd27 100644
--- a/llvm/test/MC/AMDGPU/gfx7_asm_mimg.s
+++ b/llvm/test/MC/AMDGPU/gfx7_asm_mimg.s
@@ -1026,6 +1026,57 @@ image_atomic_cmpswap v[1:2], v2, s[12:19] dmask:0x3 unorm lwe
 image_atomic_cmpswap v[1:2], v2, s[12:19] dmask:0x3 unorm da
 // CHECK: [0x00,0x53,0x40,0xf0,0x02,0x01,0x03,0x00]
 
+image_atomic_fcmpswap v[1:2], v2, s[12:19] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x74,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_fcmpswap v[254:255], v2, s[12:19] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x74,0xf0,0x02,0xfe,0x03,0x00]
+
+image_atomic_fcmpswap v[1:4], v2, s[12:19] dmask:0xf unorm
+// CHECK: [0x00,0x1f,0x74,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_fcmpswap v[252:255], v2, s[12:19] dmask:0xf unorm
+// CHECK: [0x00,0x1f,0x74,0xf0,0x02,0xfc,0x03,0x00]
+
+image_atomic_fcmpswap v[1:2], v255, s[12:19] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x74,0xf0,0xff,0x01,0x03,0x00]
+
+image_atomic_fcmpswap v[1:2], v[2:4], s[12:19] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x74,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_fcmpswap v[1:2], v[253:255], s[12:19] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x74,0xf0,0xfd,0x01,0x03,0x00]
+
+image_atomic_fcmpswap v[1:2], v[2:5], s[12:19] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x74,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_fcmpswap v[1:2], v[252:255], s[12:19] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x74,0xf0,0xfc,0x01,0x03,0x00]
+
+image_atomic_fcmpswap v[1:2], v[2:3], s[12:19] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x74,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_fcmpswap v[1:2], v[254:255], s[12:19] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x74,0xf0,0xfe,0x01,0x03,0x00]
+
+image_atomic_fcmpswap v[1:2], v2, s[96:103] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x74,0xf0,0x02,0x01,0x18,0x00]
+
+image_atomic_fcmpswap v[1:2], v2, ttmp[4:11] dmask:0x3 unorm
+// CHECK: [0x00,0x13,0x74,0xf0,0x02,0x01,0x1d,0x00]
+
+image_atomic_fcmpswap v[1:2], v2, s[12:19] dmask:0x3 unorm glc
+// CHECK: [0x00,0x33,0x74,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_fcmpswap v[1:2], v2, s[12:19] dmask:0x3 unorm slc
+// CHECK: [0x00,0x13,0x74,0xf2,0x02,0x01,0x03,0x00]
+
+image_atomic_fcmpswap v[1:2], v2, s[12:19] dmask:0x3 unorm lwe
+// CHECK: [0x00,0x13,0x76,0xf0,0x02,0x01,0x03,0x00]
+
+image_atomic_fcmpswap v[1:2], v2, s[12:19] dmask:0x3 unorm da
+// CHECK: [0x00,0x53,0x74,0xf0,0x02,0x01,0x03,0x00]
+
 image_atomic_add v1, v2, s[12:19] dmask:0x1 unorm
 // CHECK: [0x00,0x11,0x44,0xf0,0x02,0x01,0x03,0x00]
 

diff  --git a/llvm/test/MC/Disassembler/AMDGPU/gfx10_mimg.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx10_mimg.txt
index 2e625763a0a7f..01796034495bc 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/gfx10_mimg.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/gfx10_mimg.txt
@@ -1,5 +1,9 @@
 # RUN: llvm-mc -arch=amdgcn -mcpu=gfx1010 -disassemble -show-encoding < %s | FileCheck -check-prefixes=GFX10 %s
 
+#===------------------------------------------------------------------------===#
+# MIMG, regular address
+#===------------------------------------------------------------------------===#
+
 # GFX10: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm ; encoding: [0x00,0x1f,0x00,0xf0,0x00,0x00,0x00,0x00]
 0x00,0x1f,0x00,0xf0,0x00,0x00,0x00,0x00
 
@@ -166,6 +170,145 @@
 # GFX10: image_atomic_swap v16, v8, s[96:103] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm ; encoding: [0x00,0x11,0x3c,0xf0,0x08,0x10,0x18,0x00]
 0x00,0x11,0x3c,0xf0,0x08,0x10,0x18,0x00
 
+# GFX10: image_sample_c_b v[16:19], v[8:12], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_CUBE ; encoding: [0x18,0x0f,0xb4,0xf0,0x08,0x10,0x25,0x03]
+0x18,0x0f,0xb4,0xf0,0x08,0x10,0x25,0x03
+
+# GFX10: image_sample_c_b_cl v[16:19], v[250:255], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_CUBE ; encoding: [0x18,0x0f,0xb8,0xf0,0xfa,0x10,0x25,0x03]
+0x18,0x0f,0xb8,0xf0,0xfa,0x10,0x25,0x03
+
+# GFX10: image_sample_c_lz v[16:19], v[253:255], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x08,0x0f,0xbc,0xf0,0xfd,0x10,0x25,0x03]
+0x08,0x0f,0xbc,0xf0,0xfd,0x10,0x25,0x03
+
+# GFX10: image_sample_o v[16:19], v[252:255], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x28,0x0f,0xc0,0xf0,0xfc,0x10,0x25,0x03]
+0x28,0x0f,0xc0,0xf0,0xfc,0x10,0x25,0x03
+
+# GFX10: image_atomic_fcmpswap v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm ; encoding: [0x00,0x13,0x74,0xf0,0x02,0x01,0x03,0x00]
+0x00,0x13,0x74,0xf0,0x02,0x01,0x03,0x00
+
+# GFX10: image_atomic_fcmpswap v[254:255], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm ; encoding: [0x00,0x13,0x74,0xf0,0x02,0xfe,0x03,0x00]
+0x00,0x13,0x74,0xf0,0x02,0xfe,0x03,0x00
+
+# GFX10: image_atomic_fcmpswap v[1:4], v2, s[12:19] dmask:0xf dim:SQ_RSRC_IMG_1D unorm ; encoding: [0x00,0x1f,0x74,0xf0,0x02,0x01,0x03,0x00]
+0x00,0x1f,0x74,0xf0,0x02,0x01,0x03,0x00
+
+# GFX10: image_atomic_fcmpswap v[252:255], v2, s[12:19] dmask:0xf dim:SQ_RSRC_IMG_1D unorm ; encoding: [0x00,0x1f,0x74,0xf0,0x02,0xfc,0x03,0x00]
+0x00,0x1f,0x74,0xf0,0x02,0xfc,0x03,0x00
+
+# GFX10: image_atomic_fcmpswap v[1:2], v255, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm ; encoding: [0x00,0x13,0x74,0xf0,0xff,0x01,0x03,0x00]
+0x00,0x13,0x74,0xf0,0xff,0x01,0x03,0x00
+
+# GFX10: image_atomic_fcmpswap v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm a16 ; encoding: [0x00,0x13,0x74,0xf0,0x02,0x01,0x03,0x40]
+0x00,0x13,0x74,0xf0,0x02,0x01,0x03,0x40
+
+# GFX10: image_atomic_fcmpswap v[1:2], v255, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm a16 ; encoding: [0x00,0x13,0x74,0xf0,0xff,0x01,0x03,0x40]
+0x00,0x13,0x74,0xf0,0xff,0x01,0x03,0x40
+
+# GFX10: image_atomic_fcmpswap v[1:2], v[2:4], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_3D unorm ; encoding: [0x10,0x13,0x74,0xf0,0x02,0x01,0x03,0x00]
+0x10,0x13,0x74,0xf0,0x02,0x01,0x03,0x00
+
+# GFX10: image_atomic_fcmpswap v[1:2], v[253:255], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_3D unorm ; encoding: [0x10,0x13,0x74,0xf0,0xfd,0x01,0x03,0x00]
+0x10,0x13,0x74,0xf0,0xfd,0x01,0x03,0x00
+
+# GFX10: image_atomic_fcmpswap v[1:2], v[2:3], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_3D unorm a16 ; encoding: [0x10,0x13,0x74,0xf0,0x02,0x01,0x03,0x40]
+0x10,0x13,0x74,0xf0,0x02,0x01,0x03,0x40
+
+# GFX10: image_atomic_fcmpswap v[1:2], v[254:255], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_3D unorm a16 ; encoding: [0x10,0x13,0x74,0xf0,0xfe,0x01,0x03,0x40]
+0x10,0x13,0x74,0xf0,0xfe,0x01,0x03,0x40
+
+# GFX10: image_atomic_fcmpswap v[1:2], v[2:5], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm ; encoding: [0x38,0x13,0x74,0xf0,0x02,0x01,0x03,0x00]
+0x38,0x13,0x74,0xf0,0x02,0x01,0x03,0x00
+
+# GFX10: image_atomic_fcmpswap v[1:2], v[252:255], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm ; encoding: [0x38,0x13,0x74,0xf0,0xfc,0x01,0x03,0x00]
+0x38,0x13,0x74,0xf0,0xfc,0x01,0x03,0x00
+
+# GFX10: image_atomic_fcmpswap v[1:2], v[2:3], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 ; encoding: [0x38,0x13,0x74,0xf0,0x02,0x01,0x03,0x40]
+0x38,0x13,0x74,0xf0,0x02,0x01,0x03,0x40
+
+# GFX10: image_atomic_fcmpswap v[1:2], v[254:255], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 ; encoding: [0x38,0x13,0x74,0xf0,0xfe,0x01,0x03,0x40]
+0x38,0x13,0x74,0xf0,0xfe,0x01,0x03,0x40
+
+# GFX10: image_atomic_fcmpswap v[1:2], v[2:3], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_2D unorm ; encoding: [0x08,0x13,0x74,0xf0,0x02,0x01,0x03,0x00]
+0x08,0x13,0x74,0xf0,0x02,0x01,0x03,0x00
+
+# GFX10: image_atomic_fcmpswap v[1:2], v[254:255], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_2D unorm ; encoding: [0x08,0x13,0x74,0xf0,0xfe,0x01,0x03,0x00]
+0x08,0x13,0x74,0xf0,0xfe,0x01,0x03,0x00
+
+# GFX10: image_atomic_fcmpswap v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_2D unorm a16 ; encoding: [0x08,0x13,0x74,0xf0,0x02,0x01,0x03,0x40]
+0x08,0x13,0x74,0xf0,0x02,0x01,0x03,0x40
+
+# GFX10: image_atomic_fcmpswap v[1:2], v255, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_2D unorm a16 ; encoding: [0x08,0x13,0x74,0xf0,0xff,0x01,0x03,0x40]
+0x08,0x13,0x74,0xf0,0xff,0x01,0x03,0x40
+
+# GFX10: image_atomic_fcmpswap v[1:2], v[2:4], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_CUBE unorm ; encoding: [0x18,0x13,0x74,0xf0,0x02,0x01,0x03,0x00]
+0x18,0x13,0x74,0xf0,0x02,0x01,0x03,0x00
+
+# GFX10: image_atomic_fcmpswap v[1:2], v[253:255], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_CUBE unorm ; encoding: [0x18,0x13,0x74,0xf0,0xfd,0x01,0x03,0x00]
+0x18,0x13,0x74,0xf0,0xfd,0x01,0x03,0x00
+
+# GFX10: image_atomic_fcmpswap v[1:2], v[2:3], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_CUBE unorm a16 ; encoding: [0x18,0x13,0x74,0xf0,0x02,0x01,0x03,0x40]
+0x18,0x13,0x74,0xf0,0x02,0x01,0x03,0x40
+
+# GFX10: image_atomic_fcmpswap v[1:2], v[254:255], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_CUBE unorm a16 ; encoding: [0x18,0x13,0x74,0xf0,0xfe,0x01,0x03,0x40]
+0x18,0x13,0x74,0xf0,0xfe,0x01,0x03,0x40
+
+# GFX10: image_atomic_fcmpswap v[1:2], v[2:3], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY unorm ; encoding: [0x20,0x13,0x74,0xf0,0x02,0x01,0x03,0x00]
+0x20,0x13,0x74,0xf0,0x02,0x01,0x03,0x00
+
+# GFX10: image_atomic_fcmpswap v[1:2], v[254:255], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY unorm ; encoding: [0x20,0x13,0x74,0xf0,0xfe,0x01,0x03,0x00]
+0x20,0x13,0x74,0xf0,0xfe,0x01,0x03,0x00
+
+# GFX10: image_atomic_fcmpswap v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY unorm a16 ; encoding: [0x20,0x13,0x74,0xf0,0x02,0x01,0x03,0x40]
+0x20,0x13,0x74,0xf0,0x02,0x01,0x03,0x40
+
+# GFX10: image_atomic_fcmpswap v[1:2], v255, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY unorm a16 ; encoding: [0x20,0x13,0x74,0xf0,0xff,0x01,0x03,0x40]
+0x20,0x13,0x74,0xf0,0xff,0x01,0x03,0x40
+
+# GFX10: image_atomic_fcmpswap v[1:2], v[2:4], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY unorm ; encoding: [0x28,0x13,0x74,0xf0,0x02,0x01,0x03,0x00]
+0x28,0x13,0x74,0xf0,0x02,0x01,0x03,0x00
+
+# GFX10: image_atomic_fcmpswap v[1:2], v[253:255], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY unorm ; encoding: [0x28,0x13,0x74,0xf0,0xfd,0x01,0x03,0x00]
+0x28,0x13,0x74,0xf0,0xfd,0x01,0x03,0x00
+
+# GFX10: image_atomic_fcmpswap v[1:2], v[2:3], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY unorm a16 ; encoding: [0x28,0x13,0x74,0xf0,0x02,0x01,0x03,0x40]
+0x28,0x13,0x74,0xf0,0x02,0x01,0x03,0x40
+
+# GFX10: image_atomic_fcmpswap v[1:2], v[254:255], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY unorm a16 ; encoding: [0x28,0x13,0x74,0xf0,0xfe,0x01,0x03,0x40]
+0x28,0x13,0x74,0xf0,0xfe,0x01,0x03,0x40
+
+# GFX10: image_atomic_fcmpswap v[1:2], v[2:4], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA unorm ; encoding: [0x30,0x13,0x74,0xf0,0x02,0x01,0x03,0x00]
+0x30,0x13,0x74,0xf0,0x02,0x01,0x03,0x00
+
+# GFX10: image_atomic_fcmpswap v[1:2], v[253:255], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA unorm ; encoding: [0x30,0x13,0x74,0xf0,0xfd,0x01,0x03,0x00]
+0x30,0x13,0x74,0xf0,0xfd,0x01,0x03,0x00
+
+# GFX10: image_atomic_fcmpswap v[1:2], v[2:3], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA unorm a16 ; encoding: [0x30,0x13,0x74,0xf0,0x02,0x01,0x03,0x40]
+0x30,0x13,0x74,0xf0,0x02,0x01,0x03,0x40
+
+# GFX10: image_atomic_fcmpswap v[1:2], v[254:255], s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA unorm a16 ; encoding: [0x30,0x13,0x74,0xf0,0xfe,0x01,0x03,0x40]
+0x30,0x13,0x74,0xf0,0xfe,0x01,0x03,0x40
+
+# GFX10: image_atomic_fcmpswap v[1:2], v2, s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm ; encoding: [0x00,0x13,0x74,0xf0,0x02,0x01,0x18,0x00]
+0x00,0x13,0x74,0xf0,0x02,0x01,0x18,0x00
+
+# GFX10: image_atomic_fcmpswap v[1:2], v2, ttmp[8:15] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm ; encoding: [0x00,0x13,0x74,0xf0,0x02,0x01,0x1d,0x00]
+0x00,0x13,0x74,0xf0,0x02,0x01,0x1d,0x00
+
+# GFX10: image_atomic_fcmpswap v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc ; encoding: [0x00,0x33,0x74,0xf0,0x02,0x01,0x03,0x00]
+0x00,0x33,0x74,0xf0,0x02,0x01,0x03,0x00
+
+# GFX10: image_atomic_fcmpswap v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm slc ; encoding: [0x00,0x13,0x74,0xf2,0x02,0x01,0x03,0x00]
+0x00,0x13,0x74,0xf2,0x02,0x01,0x03,0x00
+
+# GFX10: image_atomic_fcmpswap v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm dlc ; encoding: [0x80,0x13,0x74,0xf0,0x02,0x01,0x03,0x00]
+0x80,0x13,0x74,0xf0,0x02,0x01,0x03,0x00
+
+# GFX10: image_atomic_fcmpswap v[1:2], v2, s[12:19] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm lwe ; encoding: [0x00,0x13,0x76,0xf0,0x02,0x01,0x03,0x00]
+0x00,0x13,0x76,0xf0,0x02,0x01,0x03,0x00
+
+#===------------------------------------------------------------------------===#
+# MIMG, NSA address
+#===------------------------------------------------------------------------===#
+
 # NOTE: Contents of unused NSA bytes are NOT preserved.
 
 # GFX10: image_atomic_cmpswap v[16:17], [v8, v9], s[96:103] dmask:0x3 dim:SQ_RSRC_IMG_2D unorm glc ; encoding: [0x0a,0x33,0x40,0xf0,0x08,0x10,0x18,0x00,0x09,0x00,0x00,0x00]
@@ -252,18 +395,6 @@
 # GFX10: image_sample_c_l v[16:19], [v8, v9, v10, v11, v12], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_CUBE ; encoding: [0x1a,0x0f,0xb0,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c]
 0x1a,0x0f,0xb0,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c
 
-# GFX10: image_sample_c_b v[16:19], v[8:12], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_CUBE ; encoding: [0x18,0x0f,0xb4,0xf0,0x08,0x10,0x25,0x03]
-0x18,0x0f,0xb4,0xf0,0x08,0x10,0x25,0x03
-
-# GFX10: image_sample_c_b_cl v[16:19], v[250:255], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_CUBE ; encoding: [0x18,0x0f,0xb8,0xf0,0xfa,0x10,0x25,0x03]
-0x18,0x0f,0xb8,0xf0,0xfa,0x10,0x25,0x03
-
-# GFX10: image_sample_c_lz v[16:19], v[253:255], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_2D ; encoding: [0x08,0x0f,0xbc,0xf0,0xfd,0x10,0x25,0x03]
-0x08,0x0f,0xbc,0xf0,0xfd,0x10,0x25,0x03
-
-# GFX10: image_sample_o v[16:19], v[252:255], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; encoding: [0x28,0x0f,0xc0,0xf0,0xfc,0x10,0x25,0x03]
-0x28,0x0f,0xc0,0xf0,0xfc,0x10,0x25,0x03
-
 # GFX10: image_sample_cl_o v[16:19], [v8, v9, v10], s[20:27], s[100:103] dmask:0xf dim:SQ_RSRC_IMG_1D ; encoding: [0x02,0x0f,0xc4,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x00,0x00]
 0x02,0x0f,0xc4,0xf0,0x08,0x10,0x25,0x03,0x09,0x0a,0x0b,0x0c

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