[llvm] af1c531 - [InstCombine] add tests for mask-shift with trunc; NFC

[Sanjay Patel via llvm-commits]

Author: Sanjay Patel
Date: 2021-09-21T09:41:41-04:00
New Revision: af1c5312d76000bf134d8b81cdb7343607c6ee64

URL: https://github.com/llvm/llvm-project/commit/af1c5312d76000bf134d8b81cdb7343607c6ee64
DIFF: https://github.com/llvm/llvm-project/commit/af1c5312d76000bf134d8b81cdb7343607c6ee64.diff

LOG: [InstCombine] add tests for mask-shift with trunc; NFC

Added: 
    

Modified: 
    llvm/test/Transforms/InstCombine/and-narrow.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/InstCombine/and-narrow.ll b/llvm/test/Transforms/InstCombine/and-narrow.ll
index 8a56f98aa691..650f29ab2a0e 100644
--- a/llvm/test/Transforms/InstCombine/and-narrow.ll
+++ b/llvm/test/Transforms/InstCombine/and-narrow.ll
@@ -2,6 +2,9 @@
 ; RUN: opt < %s -instcombine -data-layout="n8:16:32" -S | FileCheck %s
 ; RUN: opt < %s -instcombine -data-layout="n16"      -S | FileCheck %s
 
+declare void @use6(i6)
+declare void @use8(i8)
+
 ; PR35792 - https://bugs.llvm.org/show_bug.cgi?id=35792
 
 define i16 @zext_add(i8 %x) {
@@ -210,3 +213,110 @@ define <2 x i16> @zext_shl_vec_undef(<2 x i8> %x) {
   ret <2 x i16> %r
 }
 
+define i6 @trunc_lshr(i8 %x) {
+; CHECK-LABEL: @trunc_lshr(
+; CHECK-NEXT:    [[S:%.*]] = lshr i8 [[X:%.*]], 2
+; CHECK-NEXT:    [[T:%.*]] = trunc i8 [[S]] to i6
+; CHECK-NEXT:    [[R:%.*]] = and i6 [[T]], 14
+; CHECK-NEXT:    ret i6 [[R]]
+;
+  %s = lshr i8 %x, 2
+  %t = trunc i8 %s to i6
+  %r = and i6 %t, 14
+  ret i6 %r
+}
+
+define i6 @trunc_lshr_exact_mask(i8 %x) {
+; CHECK-LABEL: @trunc_lshr_exact_mask(
+; CHECK-NEXT:    [[S:%.*]] = lshr i8 [[X:%.*]], 2
+; CHECK-NEXT:    [[T:%.*]] = trunc i8 [[S]] to i6
+; CHECK-NEXT:    [[R:%.*]] = and i6 [[T]], 15
+; CHECK-NEXT:    ret i6 [[R]]
+;
+  %s = lshr i8 %x, 2
+  %t = trunc i8 %s to i6
+  %r = and i6 %t, 15
+  ret i6 %r
+}
+
+define i6 @trunc_lshr_big_mask(i8 %x) {
+; CHECK-LABEL: @trunc_lshr_big_mask(
+; CHECK-NEXT:    [[S:%.*]] = lshr i8 [[X:%.*]], 2
+; CHECK-NEXT:    [[T:%.*]] = trunc i8 [[S]] to i6
+; CHECK-NEXT:    [[R:%.*]] = and i6 [[T]], 31
+; CHECK-NEXT:    ret i6 [[R]]
+;
+  %s = lshr i8 %x, 2
+  %t = trunc i8 %s to i6
+  %r = and i6 %t, 31
+  ret i6 %r
+}
+
+define i6 @trunc_lshr_use1(i8 %x) {
+; CHECK-LABEL: @trunc_lshr_use1(
+; CHECK-NEXT:    [[S:%.*]] = lshr i8 [[X:%.*]], 2
+; CHECK-NEXT:    call void @use8(i8 [[S]])
+; CHECK-NEXT:    [[T:%.*]] = trunc i8 [[S]] to i6
+; CHECK-NEXT:    [[R:%.*]] = and i6 [[T]], 15
+; CHECK-NEXT:    ret i6 [[R]]
+;
+  %s = lshr i8 %x, 2
+  call void @use8(i8 %s)
+  %t = trunc i8 %s to i6
+  %r = and i6 %t, 15
+  ret i6 %r
+}
+
+define i6 @trunc_lshr_use2(i8 %x) {
+; CHECK-LABEL: @trunc_lshr_use2(
+; CHECK-NEXT:    [[S:%.*]] = lshr i8 [[X:%.*]], 2
+; CHECK-NEXT:    [[T:%.*]] = trunc i8 [[S]] to i6
+; CHECK-NEXT:    call void @use6(i6 [[T]])
+; CHECK-NEXT:    [[R:%.*]] = and i6 [[T]], 15
+; CHECK-NEXT:    ret i6 [[R]]
+;
+  %s = lshr i8 %x, 2
+  %t = trunc i8 %s to i6
+  call void @use6(i6 %t)
+  %r = and i6 %t, 15
+  ret i6 %r
+}
+
+define <2 x i7> @trunc_lshr_vec_splat(<2 x i16> %x) {
+; CHECK-LABEL: @trunc_lshr_vec_splat(
+; CHECK-NEXT:    [[S:%.*]] = lshr <2 x i16> [[X:%.*]], <i16 5, i16 5>
+; CHECK-NEXT:    [[T:%.*]] = trunc <2 x i16> [[S]] to <2 x i7>
+; CHECK-NEXT:    [[R:%.*]] = and <2 x i7> [[T]], <i7 1, i7 1>
+; CHECK-NEXT:    ret <2 x i7> [[R]]
+;
+  %s = lshr <2 x i16> %x, <i16 5, i16 5>
+  %t = trunc <2 x i16> %s to <2 x i7>
+  %r = and <2 x i7> %t, <i7 1, i7 1>
+  ret <2 x i7> %r
+}
+
+define <2 x i7> @trunc_lshr_vec_splat_exact_mask(<2 x i16> %x) {
+; CHECK-LABEL: @trunc_lshr_vec_splat_exact_mask(
+; CHECK-NEXT:    [[S:%.*]] = lshr <2 x i16> [[X:%.*]], <i16 6, i16 6>
+; CHECK-NEXT:    [[T:%.*]] = trunc <2 x i16> [[S]] to <2 x i7>
+; CHECK-NEXT:    [[R:%.*]] = and <2 x i7> [[T]], <i7 1, i7 1>
+; CHECK-NEXT:    ret <2 x i7> [[R]]
+;
+  %s = lshr <2 x i16> %x, <i16 6, i16 6>
+  %t = trunc <2 x i16> %s to <2 x i7>
+  %r = and <2 x i7> %t, <i7 1, i7 1>
+  ret <2 x i7> %r
+}
+
+define <2 x i7> @trunc_lshr_big_shift(<2 x i16> %x) {
+; CHECK-LABEL: @trunc_lshr_big_shift(
+; CHECK-NEXT:    [[S:%.*]] = lshr <2 x i16> [[X:%.*]], <i16 7, i16 7>
+; CHECK-NEXT:    [[T:%.*]] = trunc <2 x i16> [[S]] to <2 x i7>
+; CHECK-NEXT:    [[R:%.*]] = and <2 x i7> [[T]], <i7 1, i7 1>
+; CHECK-NEXT:    ret <2 x i7> [[R]]
+;
+  %s = lshr <2 x i16> %x, <i16 7, i16 7>
+  %t = trunc <2 x i16> %s to <2 x i7>
+  %r = and <2 x i7> %t, <i7 1, i7 1>
+  ret <2 x i7> %r
+}