[PATCH] D110164: [NVPTX] Add VRFrame and VRFrameLocal to integer register classes

Andrew Savonichev via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Sep 21 06:26:48 PDT 2021


asavonic created this revision.
asavonic added reviewers: tra, jlebar.
Herald added subscribers: hiraditya, jholewinski.
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These registers are used as operands for instructions that expect an
integer register. Machine verifier emits an error for the following
LIT tests when LLVM_ENABLE_MACHINE_VERIFIER=1 environment variable is
set:

  - Bad machine code: Illegal physical register for instruction ***
- function:    kernel_func
- basic block: %bb.0 entry (0x55c8903d5438)
- instruction: %3:int64regs = LEA_ADDRi64 $vrframelocal, 0
- operand 1:   $vrframelocal

$vrframelocal is not a Int64Regs register.

  CodeGen/NVPTX/call-with-alloca-buffer.ll
  CodeGen/NVPTX/disable-opt.ll
  CodeGen/NVPTX/lower-alloca.ll
  CodeGen/NVPTX/lower-args.ll
  CodeGen/NVPTX/param-align.ll
  CodeGen/NVPTX/reg-types.ll
  DebugInfo/NVPTX/dbg-declare-alloca.ll
  DebugInfo/NVPTX/dbg-value-const-byref.ll


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D110164

Files:
  llvm/lib/Target/NVPTX/NVPTXRegisterInfo.td


Index: llvm/lib/Target/NVPTX/NVPTXRegisterInfo.td
===================================================================
--- llvm/lib/Target/NVPTX/NVPTXRegisterInfo.td
+++ llvm/lib/Target/NVPTX/NVPTXRegisterInfo.td
@@ -56,8 +56,8 @@
 //===----------------------------------------------------------------------===//
 def Int1Regs : NVPTXRegClass<[i1], 8, (add (sequence "P%u", 0, 4))>;
 def Int16Regs : NVPTXRegClass<[i16], 16, (add (sequence "RS%u", 0, 4))>;
-def Int32Regs : NVPTXRegClass<[i32], 32, (add (sequence "R%u", 0, 4))>;
-def Int64Regs : NVPTXRegClass<[i64], 64, (add (sequence "RL%u", 0, 4))>;
+def Int32Regs : NVPTXRegClass<[i32], 32, (add (sequence "R%u", 0, 4), VRFrame, VRFrameLocal)>;
+def Int64Regs : NVPTXRegClass<[i64], 64, (add (sequence "RL%u", 0, 4), VRFrame, VRFrameLocal)>;
 def Float16Regs : NVPTXRegClass<[f16], 16, (add (sequence "H%u", 0, 4))>;
 def Float16x2Regs : NVPTXRegClass<[v2f16], 32, (add (sequence "HH%u", 0, 4))>;
 def Float32Regs : NVPTXRegClass<[f32], 32, (add (sequence "F%u", 0, 4))>;


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