[PATCH] D109323: [AArch64] Improve adrp schedule modelling on the Cortex-A55
Nicholas Guy via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 21 05:04:19 PDT 2021
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG9e4d72675f47: [AArch64] Improve schedule modelling on the Cortex-A55 (authored by NickGuy).
Changed prior to commit:
https://reviews.llvm.org/D109323?vs=371823&id=373865#toc
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D109323/new/
https://reviews.llvm.org/D109323
Files:
llvm/lib/Target/AArch64/AArch64.td
llvm/test/CodeGen/AArch64/a55-fuse-address.mir
Index: llvm/test/CodeGen/AArch64/a55-fuse-address.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/AArch64/a55-fuse-address.mir
@@ -0,0 +1,45 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -o - %s -mtriple=aarch64 -run-pass=machine-scheduler -verify-machineinstrs | FileCheck %s
+--- |
+ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
+ target triple = "aarch64-arm-none-eabi"
+
+ @a = dso_local global i32 2, align 4
+ @b = dso_local global i32 4, align 4
+
+ define i32 @fuseaddress(i32 %num) #0 {
+ entry:
+ %0 = load i32, i32* @a, align 4
+ %1 = load i32, i32* @b, align 4
+ %mul = mul nsw i32 %0, %1
+ ret i32 %mul
+ }
+
+ attributes #0 = { "target-cpu"="cortex-a55" }
+
+---
+name: fuseaddress
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+liveins:
+ - { reg: '$w0' }
+body: |
+ bb.0.entry:
+ liveins: $w0
+ ; CHECK-LABEL: name: fuseaddress
+ ; CHECK: liveins: $w0
+ ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) @a
+ ; CHECK: [[LDRWui:%[0-9]+]]:gpr32 = LDRWui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) @a :: (dereferenceable load (s32) from @a)
+ ; CHECK: [[ADRP1:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) @b
+ ; CHECK: [[LDRWui1:%[0-9]+]]:gpr32 = LDRWui [[ADRP1]], target-flags(aarch64-pageoff, aarch64-nc) @b :: (dereferenceable load (s32) from @b)
+ ; CHECK: [[MADDWrrr:%[0-9]+]]:gpr32 = nsw MADDWrrr [[LDRWui]], [[LDRWui1]], $wzr
+ ; CHECK: $w0 = COPY [[MADDWrrr]]
+ ; CHECK: RET_ReallyLR implicit $w0
+ %1:gpr64common = ADRP target-flags(aarch64-page) @a
+ %4:gpr64common = ADRP target-flags(aarch64-page) @b
+ %2:gpr32 = LDRWui killed %1:gpr64common, target-flags(aarch64-pageoff, aarch64-nc) @a :: (dereferenceable load (s32) from @a)
+ %5:gpr32 = LDRWui killed %4:gpr64common, target-flags(aarch64-pageoff, aarch64-nc) @b :: (dereferenceable load (s32) from @b)
+ %6:gpr32 = nsw MADDWrrr killed %2:gpr32, killed %5:gpr32, $wzr
+ $w0 = COPY %6:gpr32
+ RET_ReallyLR implicit $w0
Index: llvm/lib/Target/AArch64/AArch64.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64.td
+++ llvm/lib/Target/AArch64/AArch64.td
@@ -615,6 +615,7 @@
FeatureRCPC,
FeaturePerfMon,
FeaturePostRAScheduler,
+ FeatureFuseAddress,
]>;
def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
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