[PATCH] D109808: [InstCombine] Eliminate vector reverse if all inputs/outputs to an instruction are reverses

[Usman Nadeem via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGf417d9d82111: [InstCombine] Eliminate vector reverse if all inputs/outputs to an instruction… (authored by mnadeem).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109808/new/

https://reviews.llvm.org/D109808

Files:
  llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
  llvm/test/Transforms/InstCombine/vector-reverse.ll
  llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse-mask4.ll
  llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse.ll

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