[PATCH] D109301: [AMDGPU] Enable copy between VGPR and AGPR classes during regalloc

Mon Sep 20 16:41:47 PDT 2021

rampitec added inline comments.

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Comment at: llvm/test/CodeGen/AMDGPU/spill-agpr.mir:34
   ; GFX908-EXPANDED:   $vgpr0 = V_ACCVGPR_READ_B32_e64 killed $agpr0, implicit $exec
+  ; GFX908-EXPANDED:   BUFFER_STORE_DWORD_OFFSET killed $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr32, 4, 0, 0, 0, implicit $exec :: (store (s32) into %stack.1, addrspace 5)
   ; GFX908-EXPANDED:   S_NOP 0, implicit-def renamable $agpr0
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arsenm wrote:
> rampitec wrote:
> > Another obvious regression.
> This is a regression, but I think it's an acceptable one. This is using regalloc fast, so you get no optimizations. You're only losing the optimization to copy between AGPR/VGPR at -O0. The intent of the test is to stress the low level spill handling, which this still accomplishes
For fast RA it is acceptable. What about greedy? Can we do partial spill?

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Comment at: llvm/test/CodeGen/AMDGPU/spill-to-agpr-partial.mir:19
+    ; GCN: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15, $agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23, $agpr24_agpr25_agpr26_agpr27, $agpr28_agpr29, $agpr30
+    ; GCN: SCRATCH_STORE_DWORDX4_SADDR killed $vgpr0_vgpr1_vgpr2_vgpr3, $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (store (s128) into %stack.0, align 4, addrspace 5)
+    ; GCN: $vgpr0_vgpr1_vgpr2_vgpr3 = SCRATCH_LOAD_DWORDX4_SADDR $sgpr32, 0, 0, implicit $exec, implicit $flat_scr :: (load (s128) from %stack.0, align 4, addrspace 5)
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This is greedy, not fastra, the same regression.

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109301/new/

https://reviews.llvm.org/D109301