[PATCH] D109300: [AMDGPU] Make vector superclasses allocatable

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

In D109300#3010612 <https://reviews.llvm.org/D109300#3010612>, @rampitec wrote:

> Yet another question concerns gfx90a. Assume we are reading matrix C from memory into a register tuple. The mfma would need to use AGPR, but the load may use either AGPR or VGPR and has AV operand (same for a store). How likely will it happen that a VGPR tuple will be used for the load and then copied into AGPR? Can this happen?

Ideally we would have the concrete classes chosen ahead of time (i.e. regbankselect analyses the uses and defs and sets the bank, resulting in the concrete class). The main reason to make this change is to allow the allocator to split ranges with cross class copies. We wouldn't generally want AV_* classes in the incoming MIR.


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https://reviews.llvm.org/D109300