[PATCH] D109300: [AMDGPU] Make vector superclasses allocatable

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

In D109300#3010576 <https://reviews.llvm.org/D109300#3010576>, @rampitec wrote:

> Do you know how RA will chose registers for an AV operand? V, A, and AV seem to have same AllocationPriority, so what exactly RA will be doing?

You can set an explicit allocation order for a class. I think what you get now is VGPRs are higher priority than AGPRs. The real point is that RA can decide to introduce RA temporary registers to relieve pressure


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