[PATCH] D110105: Move MIParser's DBG_VALUE RegState::Debug invariant into MachineInstr::addOperand

[Jack Andersen via Phabricator via llvm-commits]

jackoalan created this revision.
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Based on the reasoning of D53903 <https://reviews.llvm.org/D53903>, register operands of `DBG_VALUE` are invariably treated as `RegState::Debug` operands. This change enforces this invariant as part of `MachineInstr::addOperand` so that all passes emit this flag consistently.

`RegState::Debug` is inconsistently set on `DBG_VALUE` registers throughout LLVM. This runs the risk of a filtering iterator like `MachineRegisterInfo::reg_nodbg_iterator` to process these operands erroneously when not parsed from MIR sources.

This issue was observed in the development of the llvm-mos fork which adds a backend that relies on physical register operands much more than existing targets. Physical RegUnit 0 has the same numeric encoding as `$noreg` (indicating an undef for DBG_VALUE). Allowing debug operands into the machine scheduler correlates `$noreg` with RegUnit 0 (i.e. a collision of register numbers with different zero semantics). Eventually, this causes an assert where `DBG_VALUE` instructions are prohibited from participating in live register ranges.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D110105

Files:
  llvm/lib/CodeGen/MIRParser/MIParser.cpp
  llvm/lib/CodeGen/MachineInstr.cpp


Index: llvm/lib/CodeGen/MachineInstr.cpp
===================================================================
--- llvm/lib/CodeGen/MachineInstr.cpp
+++ llvm/lib/CodeGen/MachineInstr.cpp
@@ -294,6 +294,9 @@
       if (MCID->getOperandConstraint(OpNo, MCOI::EARLY_CLOBBER) != -1)
         NewMO->setIsEarlyClobber(true);
     }
+    // Ensure DBG_VALUE* sets RegState::Debug on all register use operands.
+    if (NewMO->isUse() && isDebugValue())
+      NewMO->setIsDebug();
   }
 }
 
Index: llvm/lib/CodeGen/MIRParser/MIParser.cpp
===================================================================
--- llvm/lib/CodeGen/MIRParser/MIParser.cpp
+++ llvm/lib/CodeGen/MIRParser/MIParser.cpp
@@ -1011,10 +1011,6 @@
     Optional<unsigned> TiedDefIdx;
     if (parseMachineOperandAndTargetFlags(OpCode, Operands.size(), MO, TiedDefIdx))
       return true;
-    if ((OpCode == TargetOpcode::DBG_VALUE ||
-         OpCode == TargetOpcode::DBG_VALUE_LIST) &&
-        MO.isReg())
-      MO.setIsDebug();
     Operands.push_back(
         ParsedMachineOperand(MO, Loc, Token.location(), TiedDefIdx));
     if (Token.isNewlineOrEOF() || Token.is(MIToken::coloncolon) ||


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