[llvm] a95ba81 - [RISCV] Teach RISCVTargetLowering::shouldSinkOperands to sink splats for FMA.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2021-09-20T11:49:50-07:00
New Revision: a95ba8107359e17cb1669c01f416fd2723a23126

URL: https://github.com/llvm/llvm-project/commit/a95ba8107359e17cb1669c01f416fd2723a23126
DIFF: https://github.com/llvm/llvm-project/commit/a95ba8107359e17cb1669c01f416fd2723a23126.diff

LOG: [RISCV] Teach RISCVTargetLowering::shouldSinkOperands to sink splats for FMA.

If either of the multiplicands is a splat, we can sink it to use
vfmacc.vf or similar.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVISelLowering.cpp
    llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 96c0c65ba973..172c8eac0722 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1074,6 +1074,16 @@ bool RISCVTargetLowering::shouldSinkOperands(
     case Instruction::LShr:
     case Instruction::AShr:
       return Operand == 1;
+    case Instruction::Call:
+      if (auto *II = dyn_cast<IntrinsicInst>(I)) {
+        switch (II->getIntrinsicID()) {
+        case Intrinsic::fma:
+          return Operand == 0 || Operand == 1;
+        default:
+          return false;
+        }
+      }
+      return false;
     default:
       return false;
     }

diff  --git a/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll b/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
index b7c4da6b77da..7f20a67a9972 100644
--- a/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/sink-splat-operands.ll
@@ -1689,15 +1689,14 @@ define void @sink_splat_fma(float* noalias nocapture %a, float* nocapture readon
 ; CHECK-LABEL: sink_splat_fma:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    fmv.w.x ft0, a2
-; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT:    vfmv.v.f v25, ft0
 ; CHECK-NEXT:    addi a2, zero, 1024
 ; CHECK-NEXT:  .LBB26_1: # %vector.body
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    vle32.v v26, (a0)
-; CHECK-NEXT:    vle32.v v27, (a1)
-; CHECK-NEXT:    vfmacc.vv v27, v25, v26
-; CHECK-NEXT:    vse32.v v27, (a0)
+; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
+; CHECK-NEXT:    vle32.v v25, (a0)
+; CHECK-NEXT:    vle32.v v26, (a1)
+; CHECK-NEXT:    vfmacc.vf v26, ft0, v25
+; CHECK-NEXT:    vse32.v v26, (a0)
 ; CHECK-NEXT:    addi a2, a2, -4
 ; CHECK-NEXT:    addi a1, a1, 16
 ; CHECK-NEXT:    addi a0, a0, 16
@@ -1732,15 +1731,14 @@ define void @sink_splat_fma_commute(float* noalias nocapture %a, float* nocaptur
 ; CHECK-LABEL: sink_splat_fma_commute:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    fmv.w.x ft0, a2
-; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
-; CHECK-NEXT:    vfmv.v.f v25, ft0
 ; CHECK-NEXT:    addi a2, zero, 1024
 ; CHECK-NEXT:  .LBB27_1: # %vector.body
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    vle32.v v26, (a0)
-; CHECK-NEXT:    vle32.v v27, (a1)
-; CHECK-NEXT:    vfmacc.vv v27, v25, v26
-; CHECK-NEXT:    vse32.v v27, (a0)
+; CHECK-NEXT:    vsetivli zero, 4, e32, m1, ta, mu
+; CHECK-NEXT:    vle32.v v25, (a0)
+; CHECK-NEXT:    vle32.v v26, (a1)
+; CHECK-NEXT:    vfmacc.vf v26, ft0, v25
+; CHECK-NEXT:    vse32.v v26, (a0)
 ; CHECK-NEXT:    addi a2, a2, -4
 ; CHECK-NEXT:    addi a1, a1, 16
 ; CHECK-NEXT:    addi a0, a0, 16
@@ -1787,16 +1785,15 @@ define dso_local void @sink_splat_fma_scalable(float* noalias nocapture %a, floa
 ; CHECK-NEXT:    mv a3, zero
 ; CHECK-NEXT:    remu a6, t0, t1
 ; CHECK-NEXT:    sub t0, t0, a6
-; CHECK-NEXT:    vsetvli a4, zero, e32, m1, ta, mu
-; CHECK-NEXT:    vfmv.v.f v25, ft0
 ; CHECK-NEXT:  .LBB28_3: # %vector.body
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    add a4, a0, a5
+; CHECK-NEXT:    add a2, a0, a5
+; CHECK-NEXT:    vl1re32.v v25, (a2)
+; CHECK-NEXT:    add a4, a1, a5
 ; CHECK-NEXT:    vl1re32.v v26, (a4)
-; CHECK-NEXT:    add a2, a1, a5
-; CHECK-NEXT:    vl1re32.v v27, (a2)
-; CHECK-NEXT:    vfmacc.vv v27, v25, v26
-; CHECK-NEXT:    vs1r.v v27, (a4)
+; CHECK-NEXT:    vsetvli a4, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vfmacc.vf v26, ft0, v25
+; CHECK-NEXT:    vs1r.v v26, (a2)
 ; CHECK-NEXT:    add a3, a3, t1
 ; CHECK-NEXT:    add a5, a5, a7
 ; CHECK-NEXT:    bne a3, t0, .LBB28_3
@@ -1892,16 +1889,15 @@ define dso_local void @sink_splat_fma_commute_scalable(float* noalias nocapture
 ; CHECK-NEXT:    mv a3, zero
 ; CHECK-NEXT:    remu a6, t0, t1
 ; CHECK-NEXT:    sub t0, t0, a6
-; CHECK-NEXT:    vsetvli a4, zero, e32, m1, ta, mu
-; CHECK-NEXT:    vfmv.v.f v25, ft0
 ; CHECK-NEXT:  .LBB29_3: # %vector.body
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
-; CHECK-NEXT:    add a4, a0, a5
+; CHECK-NEXT:    add a2, a0, a5
+; CHECK-NEXT:    vl1re32.v v25, (a2)
+; CHECK-NEXT:    add a4, a1, a5
 ; CHECK-NEXT:    vl1re32.v v26, (a4)
-; CHECK-NEXT:    add a2, a1, a5
-; CHECK-NEXT:    vl1re32.v v27, (a2)
-; CHECK-NEXT:    vfmacc.vv v27, v25, v26
-; CHECK-NEXT:    vs1r.v v27, (a4)
+; CHECK-NEXT:    vsetvli a4, zero, e32, m1, ta, mu
+; CHECK-NEXT:    vfmacc.vf v26, ft0, v25
+; CHECK-NEXT:    vs1r.v v26, (a2)
 ; CHECK-NEXT:    add a3, a3, t1
 ; CHECK-NEXT:    add a5, a5, a7
 ; CHECK-NEXT:    bne a3, t0, .LBB29_3