[llvm] 3f90df2 - [ARM] MVE reverse shuffles.
David Green via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 20 05:48:32 PDT 2021
Author: David Green
Date: 2021-09-20T13:48:01+01:00
New Revision: 3f90df22f1b72932016102daf8e92e99252e5589
URL: https://github.com/llvm/llvm-project/commit/3f90df22f1b72932016102daf8e92e99252e5589
DIFF: https://github.com/llvm/llvm-project/commit/3f90df22f1b72932016102daf8e92e99252e5589.diff
LOG: [ARM] MVE reverse shuffles.
The vectorizer can sometimes make reverse shuffles from indices that
count down. In MVE, we don't have a 128bit rev instruction, but we can
select this to a VREV64 with some lane movs to swap the two halfs.
Ideally this would use VMOVD's, but only gets as far as VMOVS's at the
moment.
Differential Revision: https://reviews.llvm.org/D69510
Added:
Modified:
llvm/lib/Target/ARM/ARMISelLowering.cpp
llvm/test/CodeGen/Thumb2/mve-shuffle.ll
llvm/test/CodeGen/Thumb2/mve-shufflemov.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index cc66414efdd9..537249b14eec 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -8231,7 +8231,7 @@ bool ARMTargetLowering::isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const {
isVTBLMask(M, VT) ||
isNEONTwoResultShuffleMask(M, VT, WhichResult, isV_UNDEF)))
return true;
- else if (Subtarget->hasNEON() && (VT == MVT::v8i16 || VT == MVT::v16i8) &&
+ else if ((VT == MVT::v8i16 || VT == MVT::v8f16 || VT == MVT::v16i8) &&
isReverseMask(M, VT))
return true;
else if (Subtarget->hasMVEIntegerOps() &&
@@ -8324,21 +8324,23 @@ static SDValue LowerVECTOR_SHUFFLEv8i8(SDValue Op,
DAG.getBuildVector(MVT::v8i8, DL, VTBLMask));
}
-static SDValue LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(SDValue Op,
- SelectionDAG &DAG) {
+static SDValue LowerReverse_VECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
SDLoc DL(Op);
- SDValue OpLHS = Op.getOperand(0);
- EVT VT = OpLHS.getValueType();
+ EVT VT = Op.getValueType();
- assert((VT == MVT::v8i16 || VT == MVT::v16i8) &&
+ assert((VT == MVT::v8i16 || VT == MVT::v8f16 || VT == MVT::v16i8) &&
"Expect an v8i16/v16i8 type");
- OpLHS = DAG.getNode(ARMISD::VREV64, DL, VT, OpLHS);
- // For a v16i8 type: After the VREV, we have got <8, ...15, 8, ..., 0>. Now,
+ SDValue OpLHS = DAG.getNode(ARMISD::VREV64, DL, VT, Op.getOperand(0));
+ // For a v16i8 type: After the VREV, we have got <7, ..., 0, 15, ..., 8>. Now,
// extract the first 8 bytes into the top double word and the last 8 bytes
- // into the bottom double word. The v8i16 case is similar.
- unsigned ExtractNum = (VT == MVT::v16i8) ? 8 : 4;
- return DAG.getNode(ARMISD::VEXT, DL, VT, OpLHS, OpLHS,
- DAG.getConstant(ExtractNum, DL, MVT::i32));
+ // into the bottom double word, through a new vector shuffle that will be
+ // turned into a VEXT on Neon, or a couple of VMOVDs on MVE.
+ std::vector<int> NewMask;
+ for (unsigned i = 0; i < VT.getVectorNumElements() / 2; i++)
+ NewMask.push_back(VT.getVectorNumElements() / 2 + i);
+ for (unsigned i = 0; i < VT.getVectorNumElements() / 2; i++)
+ NewMask.push_back(i);
+ return DAG.getVectorShuffle(VT, DL, OpLHS, OpLHS, NewMask);
}
static EVT getVectorTyFromPredicateVector(EVT VT) {
@@ -8760,8 +8762,9 @@ static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG,
return DAG.getNode(ISD::BITCAST, dl, VT, Val);
}
- if (ST->hasNEON() && (VT == MVT::v8i16 || VT == MVT::v16i8) && isReverseMask(ShuffleMask, VT))
- return LowerReverse_VECTOR_SHUFFLEv16i8_v8i16(Op, DAG);
+ if ((VT == MVT::v8i16 || VT == MVT::v8f16 || VT == MVT::v16i8) &&
+ isReverseMask(ShuffleMask, VT))
+ return LowerReverse_VECTOR_SHUFFLE(Op, DAG);
if (ST->hasNEON() && VT == MVT::v8i8)
if (SDValue NewOp = LowerVECTOR_SHUFFLEv8i8(Op, ShuffleMask, DAG))
diff --git a/llvm/test/CodeGen/Thumb2/mve-shuffle.ll b/llvm/test/CodeGen/Thumb2/mve-shuffle.ll
index 6ede494c81ea..e7e8382336ce 100644
--- a/llvm/test/CodeGen/Thumb2/mve-shuffle.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-shuffle.ll
@@ -200,15 +200,11 @@ entry:
define arm_aapcs_vfpcc <8 x i16> @shuffle1_i16(<8 x i16> %src) {
; CHECK-LABEL: shuffle1_i16:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov q1, q0
-; CHECK-NEXT: vmovx.f16 s0, s7
-; CHECK-NEXT: vmovx.f16 s1, s6
-; CHECK-NEXT: vmovx.f16 s2, s5
-; CHECK-NEXT: vmovx.f16 s3, s4
-; CHECK-NEXT: vins.f16 s0, s7
-; CHECK-NEXT: vins.f16 s1, s6
-; CHECK-NEXT: vins.f16 s2, s5
-; CHECK-NEXT: vins.f16 s3, s4
+; CHECK-NEXT: vrev64.16 q1, q0
+; CHECK-NEXT: vmov.f32 s0, s6
+; CHECK-NEXT: vmov.f32 s1, s7
+; CHECK-NEXT: vmov.f32 s2, s4
+; CHECK-NEXT: vmov.f32 s3, s5
; CHECK-NEXT: bx lr
entry:
%out = shufflevector <8 x i16> %src, <8 x i16> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
@@ -478,39 +474,11 @@ entry:
define arm_aapcs_vfpcc <16 x i8> @shuffle1_i8(<16 x i8> %src) {
; CHECK-LABEL: shuffle1_i8:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov q1, q0
-; CHECK-NEXT: vmov.u8 r0, q0[15]
-; CHECK-NEXT: vmov.8 q0[0], r0
-; CHECK-NEXT: vmov.u8 r0, q1[14]
-; CHECK-NEXT: vmov.8 q0[1], r0
-; CHECK-NEXT: vmov.u8 r0, q1[13]
-; CHECK-NEXT: vmov.8 q0[2], r0
-; CHECK-NEXT: vmov.u8 r0, q1[12]
-; CHECK-NEXT: vmov.8 q0[3], r0
-; CHECK-NEXT: vmov.u8 r0, q1[11]
-; CHECK-NEXT: vmov.8 q0[4], r0
-; CHECK-NEXT: vmov.u8 r0, q1[10]
-; CHECK-NEXT: vmov.8 q0[5], r0
-; CHECK-NEXT: vmov.u8 r0, q1[9]
-; CHECK-NEXT: vmov.8 q0[6], r0
-; CHECK-NEXT: vmov.u8 r0, q1[8]
-; CHECK-NEXT: vmov.8 q0[7], r0
-; CHECK-NEXT: vmov.u8 r0, q1[7]
-; CHECK-NEXT: vmov.8 q0[8], r0
-; CHECK-NEXT: vmov.u8 r0, q1[6]
-; CHECK-NEXT: vmov.8 q0[9], r0
-; CHECK-NEXT: vmov.u8 r0, q1[5]
-; CHECK-NEXT: vmov.8 q0[10], r0
-; CHECK-NEXT: vmov.u8 r0, q1[4]
-; CHECK-NEXT: vmov.8 q0[11], r0
-; CHECK-NEXT: vmov.u8 r0, q1[3]
-; CHECK-NEXT: vmov.8 q0[12], r0
-; CHECK-NEXT: vmov.u8 r0, q1[2]
-; CHECK-NEXT: vmov.8 q0[13], r0
-; CHECK-NEXT: vmov.u8 r0, q1[1]
-; CHECK-NEXT: vmov.8 q0[14], r0
-; CHECK-NEXT: vmov.u8 r0, q1[0]
-; CHECK-NEXT: vmov.8 q0[15], r0
+; CHECK-NEXT: vrev64.8 q1, q0
+; CHECK-NEXT: vmov.f32 s0, s6
+; CHECK-NEXT: vmov.f32 s1, s7
+; CHECK-NEXT: vmov.f32 s2, s4
+; CHECK-NEXT: vmov.f32 s3, s5
; CHECK-NEXT: bx lr
entry:
%out = shufflevector <16 x i8> %src, <16 x i8> undef, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
@@ -1226,15 +1194,11 @@ entry:
define arm_aapcs_vfpcc <8 x half> @shuffle1_f16(<8 x half> %src) {
; CHECK-LABEL: shuffle1_f16:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov q1, q0
-; CHECK-NEXT: vmovx.f16 s0, s7
-; CHECK-NEXT: vmovx.f16 s1, s6
-; CHECK-NEXT: vmovx.f16 s2, s5
-; CHECK-NEXT: vmovx.f16 s3, s4
-; CHECK-NEXT: vins.f16 s0, s7
-; CHECK-NEXT: vins.f16 s1, s6
-; CHECK-NEXT: vins.f16 s2, s5
-; CHECK-NEXT: vins.f16 s3, s4
+; CHECK-NEXT: vrev64.16 q1, q0
+; CHECK-NEXT: vmov.f32 s0, s6
+; CHECK-NEXT: vmov.f32 s1, s7
+; CHECK-NEXT: vmov.f32 s2, s4
+; CHECK-NEXT: vmov.f32 s3, s5
; CHECK-NEXT: bx lr
entry:
%out = shufflevector <8 x half> %src, <8 x half> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
diff --git a/llvm/test/CodeGen/Thumb2/mve-shufflemov.ll b/llvm/test/CodeGen/Thumb2/mve-shufflemov.ll
index 7318ec8077de..e3261bda52e0 100644
--- a/llvm/test/CodeGen/Thumb2/mve-shufflemov.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-shufflemov.ll
@@ -35,15 +35,11 @@ entry:
define arm_aapcs_vfpcc <8 x i16> @shuffle_i16_76543210(<8 x i16> %s1, <8 x i16> %s2) {
; CHECK-LABEL: shuffle_i16_76543210:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov q1, q0
-; CHECK-NEXT: vmovx.f16 s0, s7
-; CHECK-NEXT: vmovx.f16 s1, s6
-; CHECK-NEXT: vmovx.f16 s2, s5
-; CHECK-NEXT: vmovx.f16 s3, s4
-; CHECK-NEXT: vins.f16 s0, s7
-; CHECK-NEXT: vins.f16 s1, s6
-; CHECK-NEXT: vins.f16 s2, s5
-; CHECK-NEXT: vins.f16 s3, s4
+; CHECK-NEXT: vrev64.16 q1, q0
+; CHECK-NEXT: vmov.f32 s0, s6
+; CHECK-NEXT: vmov.f32 s1, s7
+; CHECK-NEXT: vmov.f32 s2, s4
+; CHECK-NEXT: vmov.f32 s3, s5
; CHECK-NEXT: bx lr
entry:
%out = shufflevector <8 x i16> %s1, <8 x i16> %s2, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
@@ -180,39 +176,11 @@ entry:
define arm_aapcs_vfpcc <16 x i8> @shuffle_i8_fedcba9876543210(<16 x i8> %s1, <16 x i8> %s2) {
; CHECK-LABEL: shuffle_i8_fedcba9876543210:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov q1, q0
-; CHECK-NEXT: vmov.u8 r0, q0[15]
-; CHECK-NEXT: vmov.8 q0[0], r0
-; CHECK-NEXT: vmov.u8 r0, q1[14]
-; CHECK-NEXT: vmov.8 q0[1], r0
-; CHECK-NEXT: vmov.u8 r0, q1[13]
-; CHECK-NEXT: vmov.8 q0[2], r0
-; CHECK-NEXT: vmov.u8 r0, q1[12]
-; CHECK-NEXT: vmov.8 q0[3], r0
-; CHECK-NEXT: vmov.u8 r0, q1[11]
-; CHECK-NEXT: vmov.8 q0[4], r0
-; CHECK-NEXT: vmov.u8 r0, q1[10]
-; CHECK-NEXT: vmov.8 q0[5], r0
-; CHECK-NEXT: vmov.u8 r0, q1[9]
-; CHECK-NEXT: vmov.8 q0[6], r0
-; CHECK-NEXT: vmov.u8 r0, q1[8]
-; CHECK-NEXT: vmov.8 q0[7], r0
-; CHECK-NEXT: vmov.u8 r0, q1[7]
-; CHECK-NEXT: vmov.8 q0[8], r0
-; CHECK-NEXT: vmov.u8 r0, q1[6]
-; CHECK-NEXT: vmov.8 q0[9], r0
-; CHECK-NEXT: vmov.u8 r0, q1[5]
-; CHECK-NEXT: vmov.8 q0[10], r0
-; CHECK-NEXT: vmov.u8 r0, q1[4]
-; CHECK-NEXT: vmov.8 q0[11], r0
-; CHECK-NEXT: vmov.u8 r0, q1[3]
-; CHECK-NEXT: vmov.8 q0[12], r0
-; CHECK-NEXT: vmov.u8 r0, q1[2]
-; CHECK-NEXT: vmov.8 q0[13], r0
-; CHECK-NEXT: vmov.u8 r0, q1[1]
-; CHECK-NEXT: vmov.8 q0[14], r0
-; CHECK-NEXT: vmov.u8 r0, q1[0]
-; CHECK-NEXT: vmov.8 q0[15], r0
+; CHECK-NEXT: vrev64.8 q1, q0
+; CHECK-NEXT: vmov.f32 s0, s6
+; CHECK-NEXT: vmov.f32 s1, s7
+; CHECK-NEXT: vmov.f32 s2, s4
+; CHECK-NEXT: vmov.f32 s3, s5
; CHECK-NEXT: bx lr
entry:
%out = shufflevector <16 x i8> %s1, <16 x i8> %s2, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
@@ -338,15 +306,11 @@ entry:
define arm_aapcs_vfpcc <8 x half> @shuffle_f16_76543210(<8 x half> %s1, <8 x half> %s2) {
; CHECK-LABEL: shuffle_f16_76543210:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: vmov q1, q0
-; CHECK-NEXT: vmovx.f16 s0, s7
-; CHECK-NEXT: vmovx.f16 s1, s6
-; CHECK-NEXT: vmovx.f16 s2, s5
-; CHECK-NEXT: vmovx.f16 s3, s4
-; CHECK-NEXT: vins.f16 s0, s7
-; CHECK-NEXT: vins.f16 s1, s6
-; CHECK-NEXT: vins.f16 s2, s5
-; CHECK-NEXT: vins.f16 s3, s4
+; CHECK-NEXT: vrev64.16 q1, q0
+; CHECK-NEXT: vmov.f32 s0, s6
+; CHECK-NEXT: vmov.f32 s1, s7
+; CHECK-NEXT: vmov.f32 s2, s4
+; CHECK-NEXT: vmov.f32 s3, s5
; CHECK-NEXT: bx lr
entry:
%out = shufflevector <8 x half> %s1, <8 x half> %s2, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
More information about the llvm-commits
mailing list