[PATCH] D109963: [AArch64] Split bitmask immediate of bitwise AND operation

[Dave Green via Phabricator via llvm-commits]

dmgreen added a comment.

> For example, there are patterns as below.
>
>   multiclass SIMDAcrossLanesUnsignedIntrinsic<string baseOpc,
>                                               SDPatternOperator opNode>
>       : SIMDAcrossLanesIntrinsic<baseOpc, opNode> {
>   // If there is a masking operation keeping only what has been actually
>   // generated, consume it.
>   def : Pat<(i32 (and (i32 (vector_extract (insert_subvector undef,
>               (opNode (v8i8 V64:$Rn)), (i64 0)), (i64 0))), maski8_or_more)),
>         (i32 (EXTRACT_SUBREG
>           (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
>             (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
>           ssub))>;
>   def : Pat<(i32 (and (i32 (vector_extract (opNode (v16i8 V128:$Rn)), (i64 0))),
>               maski8_or_more)),
>           (i32 (EXTRACT_SUBREG
>             (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
>               (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
>             ssub))>;
>   def : Pat<(i32 (and (i32 (vector_extract (insert_subvector undef,
>               (opNode (v4i16 V64:$Rn)), (i64 0)), (i64 0))), maski16_or_more)),
>             (i32 (EXTRACT_SUBREG
>               (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
>                 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
>               ssub))>;
>   def : Pat<(i32 (and (i32 (vector_extract (opNode (v8i16 V128:$Rn)), (i64 0))),
>               maski16_or_more)),
>           (i32 (EXTRACT_SUBREG
>             (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
>               (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
>             ssub))>;
>   }
>
> As you can see, the patterns checks roughly (and (...), mask[8|16]_or_more) and it folds the `and` node. When I tried to split the bitmask immediate on ISelDAGToDAG level, I saw the cases in which above patterns does not work because the `mask[8]16]_or_more` constraint is failed.
>
> As other case, on AArch64ISelDAGToDAG, '(or (and' patterns are folded by `tryBitfieldInsertOp()`. After splitting the bitmask immediate, I saw the cases in which the `tryBitfieldInsertOp()` is failed.
>
> I have not checked all of regressions but there were more cases in which there are more instructions after splitting the bitmask immediate on ISelDAGToDAG level. In order to avoid it, I implemented the logic with `CustomInserter`.

OK I see. So when adding the code to AArch64DAGToDAGISel::Select, it happened before the tablegen patterns and we do have tablegen patterns that conflict with it. I'm a little surprised to see "_or_more" here.

Could it be done as a tblgen pattern then? That way the larger pattern should win. As far as I understand it would be a case of getting the correct ImmLeaf with a couple of xforms.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109963/new/

https://reviews.llvm.org/D109963