[PATCH] D109900: [AMDGPU] Filtering out the inactive lanes bits when lowering copy to SCC

Mon Sep 20 03:34:00 PDT 2021

alex-t added a comment.

In D109900#3007652 <https://reviews.llvm.org/D109900#3007652>, @ruiling wrote:

> IMO, it is more useful to use an end-to-end test ( from LLVM IR to assembly). We do lots of work scattered in different places to deal with boolean values. Things may change in the future, and we may move this logic to other passes.

In fact, SIFixSGPRCopies is the only pass that is affected by the change and it runs right after the instruction selection.
Anyway, if you like the *.ll more, so be it.

> Btw, I don't know why you were creating a file with the mode 755. I don't know whether it matters in a patch.

It does not matter -  just a glitch. 
The patch was created on windows and then fed to the 'git apply' on Ubuntu.
Some win2linux magic apparently.

================
Comment at: llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp:604
                     .addImm(0);
-            BuildMI(*MI.getParent(), std::next(I), I->getDebugLoc(),
-                    TII->get(AMDGPU::COPY), DstReg)
-                .addReg(SCCCopy);
+            I = BuildMI(*MI.getParent(), std::next(I), I->getDebugLoc(),
+                        TII->get(AMDGPU::COPY), DstReg)
----------------
ruiling wrote:
> I guess this is just used to skip the newly inserted instruction, no functional change?
Yes.

Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D109900/new/

https://reviews.llvm.org/D109900