[llvm] cf8fac7 - [X86][Atom] Specific uops for all IMUL/IDIV instructions
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sun Sep 19 08:59:31 PDT 2021
Author: Simon Pilgrim
Date: 2021-09-19T16:58:52+01:00
New Revision: cf8fac7d07307bc6679d60c3ad3e7a7792a2caa6
URL: https://github.com/llvm/llvm-project/commit/cf8fac7d07307bc6679d60c3ad3e7a7792a2caa6
DIFF: https://github.com/llvm/llvm-project/commit/cf8fac7d07307bc6679d60c3ad3e7a7792a2caa6.diff
LOG: [X86][Atom] Specific uops for all IMUL/IDIV instructions
Based off a mixture of llvm-exegesis captures (PR36895) and Intel AoM / Agner / InstLatX64 reports.
Added:
Modified:
llvm/lib/Target/X86/X86ScheduleAtom.td
llvm/test/tools/llvm-mca/X86/Atom/resources-x86_64.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86ScheduleAtom.td b/llvm/lib/Target/X86/X86ScheduleAtom.td
index 4c6a9397ea1fa..1087fdaa3febb 100644
--- a/llvm/lib/Target/X86/X86ScheduleAtom.td
+++ b/llvm/lib/Target/X86/X86ScheduleAtom.td
@@ -84,16 +84,16 @@ def : WriteRes<WriteRMW, [AtomPort0]>;
defm : AtomWriteResPair<WriteALU, [AtomPort01], [AtomPort0]>;
defm : AtomWriteResPair<WriteADC, [AtomPort01], [AtomPort0]>;
-defm : AtomWriteResPair<WriteIMul8, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 7, 7, [7,7], [7,7]>;
-defm : AtomWriteResPair<WriteIMul16, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 7, 8, [7,7], [8,8]>;
-defm : AtomWriteResPair<WriteIMul16Imm, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 6, 7, [6,6], [7,7]>;
-defm : AtomWriteResPair<WriteIMul16Reg, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 6, 7, [6,6], [7,7]>;
-defm : AtomWriteResPair<WriteIMul32, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 6, 7, [6,6], [7,7]>;
+defm : AtomWriteResPair<WriteIMul8, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 7, 7, [7,7], [7,7], 3, 3>;
+defm : AtomWriteResPair<WriteIMul16, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 7, 8, [7,7], [8,8], 4, 5>;
+defm : AtomWriteResPair<WriteIMul16Imm, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 6, 7, [6,6], [7,7], 2, 3>;
+defm : AtomWriteResPair<WriteIMul16Reg, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 6, 7, [6,6], [7,7], 2, 3>;
+defm : AtomWriteResPair<WriteIMul32, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 6, 7, [6,6], [7,7], 3, 4>;
defm : AtomWriteResPair<WriteIMul32Imm, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
defm : AtomWriteResPair<WriteIMul32Reg, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>;
-defm : AtomWriteResPair<WriteIMul64, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 12, 12, [12,12], [12,12]>;
-defm : AtomWriteResPair<WriteIMul64Imm, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 14, 14, [14,14], [14,14]>;
-defm : AtomWriteResPair<WriteIMul64Reg, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 12, 12, [12,12], [12,12]>;
+defm : AtomWriteResPair<WriteIMul64, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 12, 12, [12,12], [12,12], 8, 8>;
+defm : AtomWriteResPair<WriteIMul64Imm, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 14, 14, [14,14], [14,14], 7, 7>;
+defm : AtomWriteResPair<WriteIMul64Reg, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 12, 12, [12,12], [12,12], 6, 6>;
defm : X86WriteResUnsupported<WriteIMulH>;
defm : X86WriteResUnsupported<WriteIMulHLd>;
defm : X86WriteResPairUnsupported<WriteMULX32>;
@@ -105,14 +105,14 @@ defm : X86WriteRes<WriteBSWAP64, [AtomPort0], 1, [1], 1>;
defm : AtomWriteResPair<WriteCMPXCHG, [AtomPort01], [AtomPort01], 15, 15, [15]>;
defm : X86WriteRes<WriteCMPXCHGRMW, [AtomPort01, AtomPort0], 1, [1, 1], 1>;
-defm : AtomWriteResPair<WriteDiv8, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 50, 68, [50,50], [68,68]>;
-defm : AtomWriteResPair<WriteDiv16, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 50, 50, [50,50], [50,50]>;
-defm : AtomWriteResPair<WriteDiv32, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 50, 50, [50,50], [50,50]>;
-defm : AtomWriteResPair<WriteDiv64, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1],130,130,[130,130],[130,130]>;
-defm : AtomWriteResPair<WriteIDiv8, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 62, 62, [62,62], [62,62]>;
-defm : AtomWriteResPair<WriteIDiv16, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 62, 62, [62,62], [62,62]>;
-defm : AtomWriteResPair<WriteIDiv32, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 62, 62, [62,62], [62,62]>;
-defm : AtomWriteResPair<WriteIDiv64, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1],130,130,[130,130],[130,130]>;
+defm : AtomWriteResPair<WriteDiv8, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 50, 68, [50,50], [68,68], 9, 9>;
+defm : AtomWriteResPair<WriteDiv16, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 50, 50, [50,50], [50,50], 12, 12>;
+defm : AtomWriteResPair<WriteDiv32, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 50, 50, [50,50], [50,50], 12, 12>;
+defm : AtomWriteResPair<WriteDiv64, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1],130,130,[130,130],[130,130], 38, 38>;
+defm : AtomWriteResPair<WriteIDiv8, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 62, 62, [62,62], [62,62], 26, 26>;
+defm : AtomWriteResPair<WriteIDiv16, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 62, 62, [62,62], [62,62], 29, 29>;
+defm : AtomWriteResPair<WriteIDiv32, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 62, 62, [62,62], [62,62], 29, 29>;
+defm : AtomWriteResPair<WriteIDiv64, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1],130,130,[130,130],[130,130], 60, 60>;
defm : X86WriteResPairUnsupported<WriteCRC32>;
diff --git a/llvm/test/tools/llvm-mca/X86/Atom/resources-x86_64.s b/llvm/test/tools/llvm-mca/X86/Atom/resources-x86_64.s
index 574cb2b7ccce9..cad85f14a0014 100644
--- a/llvm/test/tools/llvm-mca/X86/Atom/resources-x86_64.s
+++ b/llvm/test/tools/llvm-mca/X86/Atom/resources-x86_64.s
@@ -1317,49 +1317,49 @@ xorq (%rax), %rdi
# CHECK-NEXT: 1 1 0.50 decq %rdi
# CHECK-NEXT: 1 1 1.00 * * decq (%rax)
# CHECK-NEXT: 1 1 1.00 * * lock decq (%rax)
-# CHECK-NEXT: 1 50 50.00 U divb %dil
-# CHECK-NEXT: 1 68 68.00 * U divb (%rax)
-# CHECK-NEXT: 1 50 50.00 U divw %si
-# CHECK-NEXT: 1 50 50.00 * U divw (%rax)
-# CHECK-NEXT: 1 50 50.00 U divl %edx
-# CHECK-NEXT: 1 50 50.00 * U divl (%rax)
-# CHECK-NEXT: 1 130 130.00 U divq %rcx
-# CHECK-NEXT: 1 130 130.00 * U divq (%rax)
+# CHECK-NEXT: 9 50 50.00 U divb %dil
+# CHECK-NEXT: 9 68 68.00 * U divb (%rax)
+# CHECK-NEXT: 12 50 50.00 U divw %si
+# CHECK-NEXT: 12 50 50.00 * U divw (%rax)
+# CHECK-NEXT: 12 50 50.00 U divl %edx
+# CHECK-NEXT: 12 50 50.00 * U divl (%rax)
+# CHECK-NEXT: 38 130 130.00 U divq %rcx
+# CHECK-NEXT: 38 130 130.00 * U divq (%rax)
# CHECK-NEXT: 1 32 16.00 U enter $7, $4095
-# CHECK-NEXT: 1 62 62.00 U idivb %dil
-# CHECK-NEXT: 1 62 62.00 * U idivb (%rax)
-# CHECK-NEXT: 1 62 62.00 U idivw %si
-# CHECK-NEXT: 1 62 62.00 * U idivw (%rax)
-# CHECK-NEXT: 1 62 62.00 U idivl %edx
-# CHECK-NEXT: 1 62 62.00 * U idivl (%rax)
-# CHECK-NEXT: 1 130 130.00 U idivq %rcx
-# CHECK-NEXT: 1 130 130.00 * U idivq (%rax)
-# CHECK-NEXT: 1 7 7.00 imulb %dil
-# CHECK-NEXT: 1 7 7.00 * imulb (%rax)
-# CHECK-NEXT: 1 7 7.00 imulw %di
-# CHECK-NEXT: 1 8 8.00 * imulw (%rax)
-# CHECK-NEXT: 1 6 6.00 imulw %si, %di
-# CHECK-NEXT: 1 7 7.00 * imulw (%rax), %di
-# CHECK-NEXT: 1 6 6.00 imulw $511, %si, %di
-# CHECK-NEXT: 1 7 7.00 * imulw $511, (%rax), %di
-# CHECK-NEXT: 1 6 6.00 imulw $7, %si, %di
-# CHECK-NEXT: 1 7 7.00 * imulw $7, (%rax), %di
-# CHECK-NEXT: 1 6 6.00 imull %edi
-# CHECK-NEXT: 1 7 7.00 * imull (%rax)
+# CHECK-NEXT: 26 62 62.00 U idivb %dil
+# CHECK-NEXT: 26 62 62.00 * U idivb (%rax)
+# CHECK-NEXT: 29 62 62.00 U idivw %si
+# CHECK-NEXT: 29 62 62.00 * U idivw (%rax)
+# CHECK-NEXT: 29 62 62.00 U idivl %edx
+# CHECK-NEXT: 29 62 62.00 * U idivl (%rax)
+# CHECK-NEXT: 60 130 130.00 U idivq %rcx
+# CHECK-NEXT: 60 130 130.00 * U idivq (%rax)
+# CHECK-NEXT: 3 7 7.00 imulb %dil
+# CHECK-NEXT: 3 7 7.00 * imulb (%rax)
+# CHECK-NEXT: 4 7 7.00 imulw %di
+# CHECK-NEXT: 5 8 8.00 * imulw (%rax)
+# CHECK-NEXT: 2 6 6.00 imulw %si, %di
+# CHECK-NEXT: 3 7 7.00 * imulw (%rax), %di
+# CHECK-NEXT: 2 6 6.00 imulw $511, %si, %di
+# CHECK-NEXT: 3 7 7.00 * imulw $511, (%rax), %di
+# CHECK-NEXT: 2 6 6.00 imulw $7, %si, %di
+# CHECK-NEXT: 3 7 7.00 * imulw $7, (%rax), %di
+# CHECK-NEXT: 3 6 6.00 imull %edi
+# CHECK-NEXT: 4 7 7.00 * imull (%rax)
# CHECK-NEXT: 1 5 5.00 imull %esi, %edi
# CHECK-NEXT: 1 5 5.00 * imull (%rax), %edi
# CHECK-NEXT: 1 5 5.00 imull $665536, %esi, %edi
# CHECK-NEXT: 1 5 5.00 * imull $665536, (%rax), %edi
# CHECK-NEXT: 1 5 5.00 imull $7, %esi, %edi
# CHECK-NEXT: 1 5 5.00 * imull $7, (%rax), %edi
-# CHECK-NEXT: 1 12 12.00 imulq %rdi
-# CHECK-NEXT: 1 12 12.00 * imulq (%rax)
-# CHECK-NEXT: 1 12 12.00 imulq %rsi, %rdi
-# CHECK-NEXT: 1 12 12.00 * imulq (%rax), %rdi
-# CHECK-NEXT: 1 14 14.00 imulq $665536, %rsi, %rdi
-# CHECK-NEXT: 1 14 14.00 * imulq $665536, (%rax), %rdi
-# CHECK-NEXT: 1 14 14.00 imulq $7, %rsi, %rdi
-# CHECK-NEXT: 1 14 14.00 * imulq $7, (%rax), %rdi
+# CHECK-NEXT: 8 12 12.00 imulq %rdi
+# CHECK-NEXT: 8 12 12.00 * imulq (%rax)
+# CHECK-NEXT: 6 12 12.00 imulq %rsi, %rdi
+# CHECK-NEXT: 6 12 12.00 * imulq (%rax), %rdi
+# CHECK-NEXT: 7 14 14.00 imulq $665536, %rsi, %rdi
+# CHECK-NEXT: 7 14 14.00 * imulq $665536, (%rax), %rdi
+# CHECK-NEXT: 7 14 14.00 imulq $7, %rsi, %rdi
+# CHECK-NEXT: 7 14 14.00 * imulq $7, (%rax), %rdi
# CHECK-NEXT: 1 92 46.00 U inb $7, %al
# CHECK-NEXT: 1 94 47.00 U inb %dx, %al
# CHECK-NEXT: 1 92 46.00 U inw $7, %ax
@@ -1416,14 +1416,14 @@ xorq (%rax), %rdi
# CHECK-NEXT: 1 1 1.00 * movzwq (%rax), %rdi
# CHECK-NEXT: 1 1 1.00 movslq %eax, %rdi
# CHECK-NEXT: 1 1 1.00 * movslq (%rax), %rdi
-# CHECK-NEXT: 1 7 7.00 mulb %dil
-# CHECK-NEXT: 1 7 7.00 * mulb (%rax)
-# CHECK-NEXT: 1 7 7.00 mulw %si
-# CHECK-NEXT: 1 8 8.00 * mulw (%rax)
-# CHECK-NEXT: 1 6 6.00 mull %edx
-# CHECK-NEXT: 1 7 7.00 * mull (%rax)
-# CHECK-NEXT: 1 12 12.00 mulq %rcx
-# CHECK-NEXT: 1 12 12.00 * mulq (%rax)
+# CHECK-NEXT: 3 7 7.00 mulb %dil
+# CHECK-NEXT: 3 7 7.00 * mulb (%rax)
+# CHECK-NEXT: 4 7 7.00 mulw %si
+# CHECK-NEXT: 5 8 8.00 * mulw (%rax)
+# CHECK-NEXT: 3 6 6.00 mull %edx
+# CHECK-NEXT: 4 7 7.00 * mull (%rax)
+# CHECK-NEXT: 8 12 12.00 mulq %rcx
+# CHECK-NEXT: 8 12 12.00 * mulq (%rax)
# CHECK-NEXT: 1 1 0.50 negb %dil
# CHECK-NEXT: 1 1 1.00 * * negb (%r8)
# CHECK-NEXT: 1 1 1.00 * * lock negb (%r8)
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