[PATCH] D109808: [InstCombine] Eliminate vector reverse if all inputs/outputs to an instruction are reverses

[Usman Nadeem via Phabricator via llvm-commits]

mnadeem updated this revision to Diff 373359.
mnadeem added a comment.

Address comments, handle cases where either side of the binary op is a splat and the other is a reverse.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109808/new/

https://reviews.llvm.org/D109808

Files:
  llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp
  llvm/test/Transforms/InstCombine/vector-reverse.ll
  llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse-mask4.ll
  llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse.ll

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