[PATCH] D109989: [X86] Improve i8 all-ones element insertion in pre-SSE4.1

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added inline comments.


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Comment at: llvm/lib/Target/X86/X86ISelLowering.cpp:19320
+      SDValue CstVector = DAG.getBuildVector(VT, dl, CstVectorElts);
+      return DAG.getNode(IsZeroElt ? ISD::AND : ISD::OR, dl, VT, N0, CstVector);
+    }
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craig.topper wrote:
> Is the AND case not tested? All the test changes have Or.
It appears to get handled already, so i've dropped it here.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109989/new/

https://reviews.llvm.org/D109989