[llvm] 3a587ed - [InstCombine] add vector tests for 'and' folds; NFC

[Sanjay Patel via llvm-commits]

Author: Sanjay Patel
Date: 2021-09-17T11:24:16-04:00
New Revision: 3a587ed20ffe55314223e73eff58f96f15f4d728

URL: https://github.com/llvm/llvm-project/commit/3a587ed20ffe55314223e73eff58f96f15f4d728
DIFF: https://github.com/llvm/llvm-project/commit/3a587ed20ffe55314223e73eff58f96f15f4d728.diff

LOG: [InstCombine] add vector tests for 'and' folds; NFC

Added: 
    

Modified: 
    llvm/test/Transforms/InstCombine/and.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/InstCombine/and.ll b/llvm/test/Transforms/InstCombine/and.ll
index 632b2023da5d5..1633b8f7168c3 100644
--- a/llvm/test/Transforms/InstCombine/and.ll
+++ b/llvm/test/Transforms/InstCombine/and.ll
@@ -587,6 +587,19 @@ define i64 @test36(i32 %X) {
   ret i64 %res
 }
 
+define <2 x i64> @test36_uniform(<2 x i32> %X) {
+; CHECK-LABEL: @test36_uniform(
+; CHECK-NEXT:    [[ZEXT:%.*]] = zext <2 x i32> [[X:%.*]] to <2 x i64>
+; CHECK-NEXT:    [[ZSUB:%.*]] = add nuw nsw <2 x i64> [[ZEXT]], <i64 7, i64 7>
+; CHECK-NEXT:    [[RES:%.*]] = and <2 x i64> [[ZSUB]], <i64 240, i64 240>
+; CHECK-NEXT:    ret <2 x i64> [[RES]]
+;
+  %zext = zext <2 x i32> %X to <2 x i64>
+  %zsub = add <2 x i64> %zext, <i64 7, i64 7>
+  %res = and <2 x i64> %zsub, <i64 240, i64 240>
+  ret <2 x i64> %res
+}
+
 define <2 x i64> @test36_undef(<2 x i32> %X) {
 ; CHECK-LABEL: @test36_undef(
 ; CHECK-NEXT:    [[ZEXT:%.*]] = zext <2 x i32> [[X:%.*]] to <2 x i64>
@@ -613,6 +626,19 @@ define i64 @test37(i32 %X) {
   ret i64 %res
 }
 
+define <2 x i64> @test37_uniform(<2 x i32> %X) {
+; CHECK-LABEL: @test37_uniform(
+; CHECK-NEXT:    [[ZEXT:%.*]] = zext <2 x i32> [[X:%.*]] to <2 x i64>
+; CHECK-NEXT:    [[ZSUB:%.*]] = mul nuw nsw <2 x i64> [[ZEXT]], <i64 7, i64 7>
+; CHECK-NEXT:    [[RES:%.*]] = and <2 x i64> [[ZSUB]], <i64 240, i64 240>
+; CHECK-NEXT:    ret <2 x i64> [[RES]]
+;
+  %zext = zext <2 x i32> %X to <2 x i64>
+  %zsub = mul <2 x i64> %zext, <i64 7, i64 7>
+  %res = and <2 x i64> %zsub, <i64 240, i64 240>
+  ret <2 x i64> %res
+}
+
 define <2 x i64> @test37_nonuniform(<2 x i32> %X) {
 ; CHECK-LABEL: @test37_nonuniform(
 ; CHECK-NEXT:    [[ZEXT:%.*]] = zext <2 x i32> [[X:%.*]] to <2 x i64>