[PATCH] D109927: [WIP][TLI] SimplifyDemandedVectorElts(): for `OR`, don't demand elements that are known to be all-ones in another operand

Roman Lebedev via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Sep 17 00:33:44 PDT 2021


lebedev.ri added a comment.

@RKSimon i don't believe we can emulate what D109726 <https://reviews.llvm.org/D109726> does when only looking at the `OR`,
i think we need to actually look at a blend (i.e. look past `and` and `andn` of operands),
and know what is being selected from what.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D109927/new/

https://reviews.llvm.org/D109927



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