[PATCH] D109858: [GlobalISel][AMDGPU] Add dead code elimination clean up after legalization.
Amara Emerson via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Sep 16 17:09:25 PDT 2021
aemerson updated this revision to Diff 373111.
aemerson retitled this revision from "[GlobalISel][AMDGPU] Add a -final-dce-legalizer flag to clean up dead code after legalization." to "[GlobalISel][AMDGPU] Add dead code elimination clean up after legalization.".
aemerson edited the summary of this revision.
Herald added subscribers: pengfei, atanasyan, jrtc27, sdardis.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D109858/new/
https://reviews.llvm.org/D109858
Files:
llvm/lib/CodeGen/GlobalISel/Legalizer.cpp
llvm/test/CodeGen/AArch64/GlobalISel/artifact-find-value.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-add.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-bswap.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-cmpxchg-128.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-extload.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-extract-vector-elt.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-extracts.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-fptrunc.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-inserts.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-itofp.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-merge-values.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-mul.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi-insertpt-decrement.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-sadde.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddo.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-saddsat.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift-imm-promote-dloc.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-shift.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-shuffle-vector.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssube.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubo.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-ssubsat.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-uadde.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-uaddo.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-unmerge-values.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-usube.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-usubo.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-extract.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-trunc.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-unmerge-values.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/artifact-combiner-zext.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/bug-legalization-artifact-combiner-dead-def.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-add.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-anyext.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ashr.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bitcast.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-brcond.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-bswap.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-build-vector.s16.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-concat-vectors.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-undef.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fabs.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fadd.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcanonicalize.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fcos.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fdiv.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fexp.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ffloor.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fma.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmaxnum.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fminnum.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fmul.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fneg.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fpext.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshl.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fshr.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsin.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsqrt.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-icmp.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def-s1025.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-implicit-def.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-intrinsic-round.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.d16.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2d.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-constant.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-flat.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-global.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-local.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-load-private.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-lshr.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memcpy.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memcpyinline.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memmove.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-memset.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-mul.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-phi.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sadde.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddo.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-saddsat.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sdiv.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-select.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext-inreg.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shl.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smax.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smin.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-smulo.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sshlsat.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssube.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubo.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ssubsat.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sub.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uadde.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddo.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-uaddsat.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-udiv.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umax.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umin.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulh.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-umulo.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ushlsat.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usube.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubo.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-usubsat.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
llvm/test/CodeGen/ARM/GlobalISel/arm-legalize-fp.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/bitwise.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/constants.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/global_address.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/pointers.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/trunc.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/zextLoad_and_sextLoad.mir
llvm/test/CodeGen/Mips/GlobalISel/legalizer/zext_and_sext.mir
llvm/test/CodeGen/X86/GlobalISel/legalize-ashr-scalar.mir
llvm/test/CodeGen/X86/GlobalISel/legalize-lshr-scalar.mir
llvm/test/CodeGen/X86/GlobalISel/legalize-shl-scalar.mir
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