[PATCH] D107790: [RISCV] Add a pass to recognize VLS strided loads/store from gather/scatter.

[Fraser Cormack via Phabricator via llvm-commits]

frasercrmck accepted this revision.
frasercrmck added a comment.
This revision is now accepted and ready to land.

LGTM with one nit. I don't know if @rogfer01 wants to give it a second look?



================
Comment at: llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp:349
+  unsigned IncrementingBlock = BasePhi->getOperand(0) == Inc ? 0 : 1;
+    assert(BasePhi->getIncomingValue(IncrementingBlock) == Inc &&
+           "Expected one operand of phi to be Inc");
----------------
This clang-format should be addressed.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D107790/new/

https://reviews.llvm.org/D107790