[PATCH] D109827: AArch64: use ldp/stp for 128-bit atomic load/store with v8.4

[Tim Northover via Phabricator via llvm-commits]

t.p.northover marked 2 inline comments as done.
t.p.northover added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:16326
+  SDValue Base, Offset;
+  matchLDPSTPAddrMode(MN->getBasePtr(), Base, Offset, DAG);
+
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t.p.northover wrote:
> efriedma wrote:
> > Would it make sense to add an AArch64ISD node to use here, instead of doing instruction selection early?
> Good idea. That should let us use `SelectAddrMode...` from ISelDAGToDAG instead of reinventing it here.
Actually, it looks like someone has beaten me to it with volatile load/store, and I was wrong about not being able to hook into LegalizeTypes. I should be able to reuse most of their work.


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  https://reviews.llvm.org/D109827/new/

https://reviews.llvm.org/D109827